MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 333

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

associated SDRAM. The primary cycle of the transfer generates the
commands; secondary cycles generate only
completes, the
Note that in synchronous operation, burst mode and address incrementing during burst cycles are
controlled by the MCF5271 DRAM controller. Thus, instead of the SDRAM enabling its internal
burst incrementing capability, the MCF5271 controls this function. This means that the burst
function that is enabled in the mode register of SDRAMs must be disabled when interfacing to the
MCF5271.
Figure 18-6
SD_SRAS-to-SD_SCAS delay (t
CAS latency (SD_SCAS assertion to data out), this value is also 2 system clock cycles. Notice that
NOP
data transfer.
Figure 18-7
an SD_SRAS-to-SD_SCAS delay (t
SD_SCAS assertion and a burst write cycle completes two cycles sooner than a burst read cycle
with the same t
the precharge-to-
Freescale Semiconductor
s are executed until the last data is read. A
SD_CS[0] or [1]
SD_SRAS
SD_SCAS
SYSCLK
SD_WE
shows the burst write operation. In this example, DACR[CASL] = 01, which creates
A[31:0]
D[31:0]
BS[3:0]
shows a burst read operation. In this example, DACR[CASL] = 01 for an
RCD.
PALL
ACTV
The next bus cycle is initiated sooner, but cannot begin an SDRAM cycle until
command is generated to prepare for the next access.
delay completes.
t
RCD
ACTV
Row
Figure 18-6. Burst Read SDRAM Access
= 2
NOP
RCD
MCF5271 Reference Manual, Rev. 2
Column Column Column
RCD
) of 2 system clock cycles. Because t
READ
) of 2 system clock cycles. Note that data is available upon
t
CASL
READ
READ
PALL
= 2
or
command is executed one cycle after the last
READ
WRITE
Column
commands. As soon as the transfer
READ
NOP
ACTV
t
Memory Map/Register Definition
RCD
EP
NOP
and
is equal to the read
READ
PALL
or
WRITE
18-15