MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 488

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

I
25.6.2 Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the
master transmitter mode. On a multiple-master bus system, I2SR[IBB] must be tested to determine
whether the serial bus is free. If the bus is free (IBB = 0), the START signal and the first byte (the
slave address) can be sent. The data written to the data register comprises the address of the desired
slave and the lsb indicates the transfer direction.
The free time between a STOP and the next START condition is built into the hardware that
generates the START cycle. Depending on the relative frequencies of the system clock and the
I2C_SCL period, it may be necessary to wait until the I
to the I2DR before proceeding with the following instructions.
The following example signals START and transmits the first byte of data (slave address):
CHFLAG
TXSTART MOVE.B I2CR,-(A0)
IFREE
25.6.3 Post-Transfer Software Response
Sending or receiving a byte sets the I2SR[ICF], which indicates one byte communication is
finished. I2SR[IIF] is also set. An interrupt is generated if the interrupt function is enabled during
initialization by setting I2CR[IIEN]. Software must first clear I2SR[IIF] in the interrupt routine.
I2SR[ICF] is cleared either by reading from I2DR in receive mode or by writing to I2DR in
transmit mode.
Software can service the I
is disabled. Polling should monitor IIF rather than ICF because that operation is different when
arbitration is lost.
When an interrupt occurs at the end of the address cycle, the master is always in transmit mode;
that is, the address is sent. If master receive mode is required I2CR[MTX] should be toggled.
25-14
2
C Interface
MOVE.B I2SR,-(A0)
BTST.B #5, (A0)+
BNE.S CHFLAG
BSET.B #4,(A0)
MOVE.B (A0)+, I2CR
MOVE.B I2CR, -(A0)
BSET.B #5, (A0)
MOVE.B (A0)+, I2CR
MOVE.B CALLING,-(A0)
MOVE.B (A0)+, I2DR
MOVE.B I2SR,-(A0)
BTST.B #5, (A0)+
BEQ.S IFREE;
2
C I/O in the main program by monitoring IIF if the interrupt function
MCF5271 Reference Manual, Rev. 2
;Check I2SR[MBB]
;If I2SR[MBB] = 1, wait until it is clear
;Set transmit mode
;Set master mode
;Generate START condition
;Transmit the calling address, D0=R/W
;Check I2SR[MBB]
;If it is clear, wait until it is set.
2
C is busy after writing the calling address
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