MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 362

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.2.4.9 Receive Control Register (RCR)
The RCR, programmed by the user, controls the operational mode of the receive block and should
be written only when ECR[ETHER_EN] = 0 (initialization time).
19-18
Address
Reset
Reset
31–27
26–16
15–6
Bits
W
W
R
R
5
4
3
2
1
0
31
15
0
0
0
0
MII_MODE Media independent interface mode. Selects external interface mode. Setting this bit to one
MAX_FL
BC_REJ
PROM
30
14
Name
LOOP
0
0
0
0
FCE
DRT
—
—
29
13
0
0
0
0
Figure 19-10. Receive Control Register (RCR)
Reserved, should be cleared.
Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and
includes the CRC at the end of the frame. Transmit frames longer than MAX_FL will cause
the BABT interrupt to occur. Receive Frames longer than MAX_FL will cause the BABR
interrupt to occur and will set the LG bit in the end of frame receive buffer descriptor. The
recommended default value to be programmed by the user is 1518 or 1522 (if VLAN Tags
are supported).
Reserved, should be cleared.
Flow control enable. If asserted, the receiver will detect PAUSE frames. Upon PAUSE
frame detection, the transmitter will stop transmitting data frames for a given duration.
Broadcast frame reject. If asserted, frames with DA (destination address) =
FF_FF_FF_FF_FF_FF will be rejected unless the PROM bit is set. If both BC_REJ and
PROM = 1, then frames with broadcast DA will be accepted and the M (MISS) bit will be
set in the receive buffer descriptor.
Promiscuous mode. All frames are accepted regardless of address matching.
selects MII mode, setting this bit equal to zero selects 7-wire mode (used only for serial 10
Mbps). This bit controls the interface mode for both transmit and receive blocks.
Disable receive on transmit.
0 Receive path operates independently of transmit (use for full duplex or to monitor
1 Disable reception of frames while transmitting (normally used for half duplex mode).
Internal loopback. If set, transmitted frames are looped back internal to the device and the
transmit output signals are not asserted. The system clock is substituted for the ETXCLK
when LOOP is asserted. DRT must be set to zero when asserting LOOP.
transmit activity in half duplex mode).
28
12
0
0
0
0
Table 19-13. RCR Field Descriptions
27
11
0
0
0
0
MCF5271 Reference Manual, Rev. 2
26
10
1
0
0
25
0
0
0
9
IPSBAR + 0x1084
24
1
0
0
8
23
1
7
0
0
Description
22
1
0
0
6
MAX_FL
FCE BC_
21
1
5
0
REJ
20
0
0
4
PROM MII_
19
1
0
3
Freescale Semiconductor
MODE
18
1
0
2
DRT LOOP
17
1
0
1
16
0
0
1