MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 143

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
31–27
26–24
23–22
21–19
Bits
18
17
Reserved
MFD[2:0]
LOCEN
LOLRE
Name
RFD
—
Multiplication factor divider. The MFD bits control the value of the divider in the PLL
feedback loop. The value specified by the MFD bits establish the multiplication factor
applied to the reference frequency. The bit field encoding is shown in row one of the table
below.
Note: Frequency modulation should be disabled (see DEPTH bits) prior to making a
change to the MFD.
Reserved
Reduced frequency divider field. The binary value written to RFD[2:0] is the PLL frequency
divisor. See table in MFD bit description. Changing RFD[2:0] does not affect the PLL or
cause a relock delay. Changes in clock frequency are synchronized to the next falling edge
of the current core clock. To avoid surpassing the allowable core operating frequency, write
to RFD[2:0] only when the LOCK bit is set.
Note: In external clock mode, the RFD bits have no affect.
Enables the loss-of-clock function. LOCEN does not affect the loss-of-lock function.
0 Loss-of-clock function disabled
1 Loss-of-clock function enabled
Note: In external clock mode, the LOCEN bit has no effect
Loss-of-lock reset enable. This bit determines how the integration module handles a
loss-of-lock indication. When operation in normal or 1:1 mode, the PLL must be locked
before setting the LOLRE bit. Otherwise reset is immediately asserted.
0 Ignore loss-of-clock – no reset
1 Reset on loss-of-lock
Note: In external clock mode, the LOLRE bit has no effect
The following table illustrates the system frequency multiplier of the reference
frequency
1
2
3
Table 7-5. SYNCR Field Descriptions
f
MFD = 000 not valid for f
Default value out of reset
sys
000 (÷ 1)
001 (÷ 2)
010 (÷ 4)
011 (÷ 8)
100 (÷ 16)
101 (÷ 32)
110 (÷ 64)
111 (÷ 128)
= f
MCF5271 Reference Manual, Rev. 2
ref
1
in normal PLL mode.
× 2(MFD + 2)/2
3
000
1/16
1/32
(4x)
1/2
1/4
1/8
4
2
1
2
RFD
ref
(6x)
3/16
3/32
3/64
001
3/2
3/4
3/8
< 3 MHz
6
3
; f
(3)
ref
Description
× 2(MFD + 2) ≤ 150MHz, f
1/16
(8x)
010
1/2
1/4
1/8
8
4
2
1
(10x)
5/16
5/32
5/64
011
MFD[2:0]
5/2
5/4
5/8
10
5
(12x)
3/16
3/32
100
3/2
3/4
3/8
12
6
3
.
.
(14x)
Memory Map/Register Definition
7/16
7/32
7/64
101
7/2
7/4
7/8
14
sys/2
7
≤ 75MHz
(16x)
110
1/2
1/4
1/8
16
8
4
2
1
(18x)
9/64
9/16
9/32
111
9/2
9/4
9/8
18
9
7-9