MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 239

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

12.3.1.5.6 FEC/I2C Pin Assignment Register (PAR_FECI2C)
The PAR_FECI2C register controls the functions of the I
Freescale Semiconductor
Bits
7–6
1–0
5
4
3
2
PAR_CSSDC
PAR_SDWE
PAR_SDCS
PAR_SCAS
PAR_SRAS
PAR_SCKE
Name
S
Table 12-13. PAR_SDRAM Field Descriptions
CS[3:2] pin primary function selection. The PAR_CSSDCS field configures each of the
CS[3:2] pins for one of its primary functions (either EIM chip select or SDRAMC chip select)
when the PAR_CS[3:2] bits are 1s. The PAR_CSSDCS values have no effect on the
CS[3:2] pin functions when the PAR_CS[3:2] bits are 0s. Refer to
Select Pin Assignment Register
SD_WE pin assignment. This bit configures the SD_WE pin for its primary function or
GPIO.
0 SD_WE pin configured for GPIO
1 SD_WE pin configured for SDRAMC WE function
SD_SCAS pin assignment. This bit configures the SD_SCAS pin for its primary function or
GPIO.
0 SD_SCAS pin configured for GPIO
1 SD_SCAS pin configured for SDRAMC CAS function
SD_SRAS pin assignment. This bit configures the SD_SRAS pin for its primary function or
GPIO.
0 SD_SRAS pin configured for GPIO
1 SD_SRAS pin configured for SDRAMC SRAS function
SD_CKE pin assignment. This bit configures the SD_CKE pin for its primary function or
GPIO.
0 SD_CKE pin configured for GPIO
1 SD_CKE pin configured for SDRAMC clock enable function
SD_CS[1:0] pin assignment. These bits configure the SD_CS[1:0] pins for their primary
functions or GPIO.
0 SD_CS[1:0] pin configured for GPIO
1 SD_CS[1:0] pin configured for SD_CS[1:0] function
MCF5271 Reference Manual, Rev. 2
Note: Only valid when PAR_CS[3:2] = 1.
00
01
10
11
(PAR_CS),” for more information on the PAR_CS bits.
Description
SD_CS1
SD_CS1
2
C and FEC pins.
CS3
CS3
CS3
SD_CS0
SD_CS0
CS2
CS2
CS2
Memory Map/Register Definition
Section 12.3.1.5.4, “Chip
12-23