MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 396

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MCF5270CAB100

Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5270CAB100

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Watchdog Timer Module
20.1.2 Block Diagram
20.2
This subsection describes the memory map and registers for the watchdog timer. The watchdog
timer has a IPSBAR offset for base address of 0x14_0000. Refer to
the watchdog memory map.
20.2.1 Register Description
The watchdog timer programming model consists of these registers:
20-2
1
• Watchdog control register (WCR), which configures watchdog timer operation
• Watchdog modulus register (WMR), which determines the timer modulus
• Watchdog count register (WCNTR), which provides visibility to the watchdog counter
IPSBAR Offset
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
0x14_0000
0x14_0004
reload value
value
Memory Map/Register Definition
Internal Bus
Clock
Watchdog Count Register (WCNTR)
Watchdog Control Register (WCR)
Table 20-2. Watchdog Timer Module Memory Map
[31:24]
Figure 20-1. Watchdog Timer Block Diagram
Divide by
HALTED
DOZE
WAIT
4096
EN
16-bit WCNTR
MCF5271 Reference Manual, Rev. 2
[23:16]
16-bit Watchdog Counter
Internal Bus
Internal Bus
16-bit WMR
Watchdog Modulus Register (WMR)
Watchdog Service Register (WSR)
[15:8]
Load Counter
16-bit WSR
Count = 0
Table 20-2
[7:0]
Freescale Semiconductor
Reset
for an overview of
Access
S/U
S
1

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