MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 588

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Debug Support
The breakpoint status is also posted in the CSR. Note that CSR[BSTAT] is cleared by a CSR read
when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2
breakpoint is not enabled. Status is also cleared by writing to TDR.
BDM instructions use the appropriate registers to load and configure breakpoints. As the system
operates, a breakpoint trigger generates the response defined in TDR.
PC breakpoints are treated in a precise manner—exception recognition and processing are initiated
before the excepting instruction is executed. All other breakpoint events are recognized on the
processor’s local bus, but are made pending to the processor and sampled like other interrupt
conditions. As a result, these interrupts are imprecise.
In systems that tolerate the processor being halted, a BDM-entry can be used. With
TDR[TRC] = 01, a breakpoint trigger causes the core to halt (PST = 0xF).
If the processor core cannot be halted, the debug interrupt can be used. With this configuration,
TDR[TRC] = 10, the breakpoint trigger becomes a debug interrupt to the processor, which is
treated higher than the nonmaskable level-7 interrupt request. As with all interrupts, it is made
pending until the processor reaches a sample point, which occurs once per instruction. Again, the
hardware forces the PC breakpoint to occur before the targeted instruction executes. This is
possible because the PC breakpoint is enabled when interrupt sampling occurs. For address and
data breakpoints, reporting is considered imprecise because several instructions may execute after
the triggering address or data is detected.
As soon as the debug interrupt is recognized, the processor aborts execution and initiates exception
processing. This event is signaled externally by the assertion of a unique PST value (PST = 0xD)
for multiple cycles. The core enters emulator mode when exception processing begins. After the
standard 8-byte exception stack is created, the processor fetches a unique exception vector, 12,
from the vector table.
Execution continues at the instruction address in the vector corresponding to the breakpoint
triggered. All interrupts are ignored while the processor is in emulator mode. The debug interrupt
handler can use supervisor instructions to save the necessary context such as the state of all
program-visible registers into a reserved memory area.
30-38
1
Table 30-22. DDATA[3:0]/CSR[BSTAT] Breakpoint Response
Encodings not shown are reserved for future use.
DDATA[3:0]
0000
0010
0100
1010
1100
1
CSR[BSTAT]
MCF5271 Reference Manual, Rev. 2
0000
0001
0010
0101
0110
1
No breakpoints enabled
Waiting for level-1 breakpoint
Level-1 breakpoint triggered
Waiting for level-2 breakpoint
Level-2 breakpoint triggered
Breakpoint Status
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