MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 209

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

11.3.2.2 Fixed Mode
In fixed arbitration the master with highest priority (as specified by the MPARK[Mn_PRTY] bits)
will win the bus. That master will relinquish the bus when all transfers to that master are complete.
If MPARK[TIMEOUT] is set, a counter will increment for each master for every cycle it is denied
access. When a counter reaches the limit set by MPARK[LCKOUT_TIME], the arbitration
algorithm will be changed to round-robin arbitration mode until all locks are cleared. The
arbitration will then return to fixed mode and the highest priority master will be granted the bus.
As in round-robin mode, if no masters are requesting, the arbitration pointer will park on the
highest priority master if MPARK[PRK_LAST] is set, or will park on the master which last
requested the bus if cleared.
11.3.3 Bus Master Park Register (MPARK)
The MPARK controls the operation of the system bus arbitration module. The platform bus master
connections are defined as:
Freescale Semiconductor
Address
• Master 3 (M3): Fast Ethernet Controller
• Master 2 (M2): 4-channel DMA
• Master 1 (M1): Reserved
• Master 0 (M0): V2 ColdFire Core
Reset
Reset
31–26
W
W
Bits
R
R
25
31
15
0
0
0
0
FIXED TIME
M2_P_EN
30
14
0
0
0
Name
—
Figure 11-7. Default Bus Master Park Register (MPARK)
OUT
29
13
0
1
0
Reserved, should be cleared.
DMA bandwidth control enable
0 disable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
1 enable the use of the DMA's bandwidth control to elevate the priority of its bus requests.
LAST
PRK
28
12
0
1
0
Table 11-6. MPARK Field Description
27
11
0
0
0
MCF5271 Reference Manual, Rev. 2
LCKOUT_TIME
26
10
0
0
0
M2_P
_EN
25
0
0
9
IPSBAR + 0x01C
24
0
0
0
8
Description
M3_PRTY
23
1
0
0
7
22
1
0
0
6
M2_PRTY
21
1
0
0
5
20
0
0
0
4
M0_PRTY
19
0
0
0
3
Internal Bus Arbitration
18
0
0
0
2
17
0
0
1
0
0
16
0
1
0
0
0
11-11