MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 356

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.2.4.4 Transmit Descriptor Active Register (TDAR)
The TDAR is a command register which should be written by the user to indicate that the transmit
descriptor ring has been updated (transmit buffers have been produced by the driver with the ready
bit set in the buffer descriptor).
Whenever the register is written, the TDAR bit is set. This value is independent of the data actually
written by the user. When set, the FEC will poll the transmit descriptor ring and process transmit
frames (provided ECR[ETHER_EN] is also set). Once the FEC polls a transmit descriptor whose
ready bit is not set, then the FEC will clear the TDAR bit and cease transmit descriptor ring polling
until the user sets the bit again, signifying additional descriptors have been placed into the transmit
descriptor ring.
The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET]
is set.
19-12
Address
Reset
Reset
31–25
23–0
Bits
24
W
W
R
R
31
15
0
0
0
0
RDAR
Name
30
14
0
0
0
0
Figure 19-4. Receive Descriptor Active Register (RDAR)
—
—
29
13
0
0
0
0
Reserved, should be cleared.
Set to one when this register is written, regardless of the value written. Cleared by the FEC
device whenever no additional “empty” descriptors remain in the receive ring. Also cleared
when ECR[ETHER_EN] is cleared.
Reserved, should be cleared.
28
12
0
0
0
0
Table 19-6. RDAR Field Descriptions
27
11
0
0
0
0
MCF5271 Reference Manual, Rev. 2
26
10
0
0
0
0
25
0
0
0
0
9
IPSBAR + 0x1010
RDAR
24
0
0
0
8
Description
23
0
0
7
0
0
22
0
0
0
0
6
21
0
0
0
0
5
20
0
0
0
0
4
19
0
0
0
0
3
Freescale Semiconductor
18
0
0
0
0
2
17
0
0
0
0
1
16
0
0
0
0
0