MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 291
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 16
Chip Select Module
16.1 Introduction
This chapter describes the chip select module, including the operation and programming model of
the chip select registers, which include the chip select address, mask, and control registers.
16.1.1 Overview
The following list summarizes the key chip select features:
16.2 External Signal Description
This section describes the signals used by the chip select module.
16.2.1 Chip Selects (CS[7:0])
Each CSn can be independently programmed for an address location as well as for masking, port
size, read/write burst capability, wait-state generation, and internal/external termination. Only CS0
is initialized at reset and may act as an external boot chip select to allow boot ROM to be at an
external address space. Port size for CS0 is configured by the logic levels of D[20:19] when
RSTOUT negates and RCON is asserted.
16.2.2 Output Enable (OE)
Interfaces to memory or to peripheral devices and enables a read transfer. It is asserted and negated
on the falling edge of the clock. OE is asserted only when one of the chip selects matches for the
current address decode.
Freescale Semiconductor
• Eight independent, user-programmable chip select signals (CS[7:0]) that can interface with
• Address masking for 64-Kbyte to 4-Gbyte memory block sizes
• Enhanced secondary wait states
• Access error on writes to write-protect (WP) region
external SRAM, PROM, EPROM, EEPROM, Flash, and peripherals
Unless otherwise noted, in this chapter, “clock” refers to the CLKOUT
used for the bus (f
sys/2
MCF5271 Reference Manual, Rev. 2
).
NOTE
16-1
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