MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 76

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
All ColdFire processors use an instruction restart exception model, but certain microarchitectures
(V2 and V3) require more software support to recover from certain access errors. See
Section 3.7.1, “Access Error
Exception processing includes all actions from the detection of the fault condition to the initiation
of fetch for the first handler instruction. Exception processing is comprised of four major steps
First, the processor makes an internal copy of the SR and then enters supervisor mode by asserting
the S bit and disabling trace mode by negating the T bit. The occurrence of an interrupt exception
also forces the M bit to be cleared and the interrupt priority mask to be set to the level of the current
interrupt request.
Second, the processor determines the exception vector number. For all faults except interrupts, the
processor performs this calculation based on the exception type. For interrupts, the processor
performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the
interrupt controller. The IACK cycle is mapped to a special acknowledge address space with the
interrupt level encoded in the address.
Third, the processor saves the current context by creating an exception stack frame on the
supervisor system stack. As a result, the exception stack frame is created at a 0-modulo-4 address
on the top of the current system stack. Additionally, the processor uses a simplified fixed-length
stack frame for all exceptions. The exception type determines whether the program counter placed
in the exception stack frame defines the location of the faulting instruction (fault) or the address
of the next instruction to be executed (next).
Fourth, the processor calculates the address of the first instruction of the exception handler. By
definition, the exception vector table is aligned on a 1 Mbyte boundary. This instruction address
is generated by fetching an exception vector from the table located at the address defined in the
vector base register. The index into the exception table is calculated as (4 x vector number). Once
the exception vector has been fetched, the contents of the vector determine the address of the first
instruction of the desired handler. After the instruction fetch for the first opcode of the handler has
been initiated, exception processing terminates and normal instruction processing continues in the
handler.
All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address
boundary (see
Freescale and the remaining 192 are user-defined interrupt vectors.
3-10
Table
Number(s)
Vector
0
1
2
3-7). The table contains 256 exception vectors; the first 64 are defined by
Table 3-7. Exception Vector Assignments
Exception” for details.
Offset (Hex)
Vector
0x000
0x004
0x008
MCF5271 Reference Manual, Rev. 2
Program
Stacked
Counter
Fault
—
—
Initial program counter
Initial stack pointer
Assignment
Access error
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