MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 553

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

displayed (debug data, DDATA). The processor status may not be related to the current bus
transfer.
External development systems can use PST outputs with an external image of the program to
completely track the dynamic execution path. This tracking is complicated by any change in flow,
especially when branch target address calculation is based on the contents of a program-visible
register (variant addressing). DDATA outputs can be configured to display the target address of
such instructions in sequential nibble increments across multiple processor clock cycles, as
described in
elements form a FIFO buffer connecting the processor’s high-speed local bus to the external
development system through PST[3:0] and DDATA[3:0]. The buffer captures branch target
addresses and certain data values for eventual display on the DDATA port, one nibble at a time
starting with the least significant bit (lsb).
Execution speed is affected only when both storage elements contain valid data to be dumped to
the DDATA port. The core stalls until one FIFO entry is available.
Table 30-2
Freescale Semiconductor
Hex
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
PST[3:0]
Binary
0000
0001
0010
0100
0101
0011
0110
0111
shows the encoding of these signals.
Section 30.3.1, “Begin Execution of Taken Branch (PST =
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more
processor clock cycles, subsequent clock cycles are indicated by driving PST outputs with this
encoding.
Begin execution of one instruction. For most instructions, this encoding signals the first processor
clock cycle of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and
WDDATA instructions, generate different encodings.
Reserved
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor
to enter user mode.
Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for
debug and/or performance analysis. WDDATA lets the core write any operand (byte, word, or
longword) directly to the DDATA port, independent of debug module configuration. When WDDATA is
executed, a value of 0x4 is signaled on the PST port, followed by the appropriate marker, and then the
data transfer on the DDATA port. Transfer length depends on the WDDATA operand size.
Begin execution of taken branch. For some opcodes, a branch target address may be displayed on
DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
indicated by the PST marker value preceding the DDATA nibble that begins the data output. See
Section 30.3.1, “Begin Execution of Taken Branch (PST =
Reserved
Begin execution of return from exception (RTE) instruction.
Table 30-2. Processor Status Encoding
MCF5271 Reference Manual, Rev. 2
Definition
0x5).”
0x5).” Two 32-bit storage
Real-Time Trace Support
30-3