MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 342
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MCF5270CAB100
Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CAB100
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Synchronous DRAM Controller Module
18.4.5 Mode Register Initialization
When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is
read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding
MCF5271 address pins must be determined while being aware of masking requirements.
Table 18-30
Next, this information is mapped to an address to determine the hexadecimal value.
Although A[31:20] corresponds to the address programmed in DACR0, according to how DACR0
and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before the mode register
bit is set, DMR0[19] must be set to enable masking.
18-24
Setting
Setting
(hex)
(hex)
Field
Field
lists the desired initialization setting:
31
15
0
x
Table 18-31. Mode Register Mapping to MCF5271 A[31:0]
30
14
x
0
MCF5271 Pins
0
0
29
13
x
0
A20
A19
A18
A17
A10
A11
A12
A13
A14
A15
A9
Table 18-30. Mode Register Initialization
28
12
x
0
27
11
1
x
MCF5271 Reference Manual, Rev. 2
SDRAM Pins
26
10
0
x
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
8
25
x
0
9
24
x
x
8
Mode Register Initialization
Reserved
Opmode
Opmode
CASL
CASL
CASL
23
x
x
7
WB
BT
BL
BL
BL
22
x
6
x
0
0
21
x
5
x
20
x
x
4
X
0
0
0
0
0
1
0
0
0
0
19
0
x
3
Freescale Semiconductor
18
0
2
x
0
0
17
0
1
x
16
V
x
0
x
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