MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 621

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
I
interrupt controller
JTAG
MDHA
power management
QSPI
reset controller
RNG
2
C
port clear output data (PCLRR_x) 12-16
port data direction (PDDR_x) 12-12
port output data (PODR_x) 12-10
port pin data/set data (PPDSDR_x) 12-14
address (I2ADR) 25-8
control (I2CR) 25-10
data I/O (I2DR) 25-12
frequency divider (I2FDR) 25-9
status (I2SR) 25-11
interrupt acknowledge level and priority
interrupt control (ICRnx) 13-12
interrupt force high/low (INTFRCHn,
interrupt pending high/low (IPRHn, IPRLn) 13-6
interrupt request level (IRLRn) 13-11
mask high/low (IMRHn, n) 13-7
bypass 29-6
IDCODE 29-5
instruction shift (IR) 29-5
TEST_CTRL 29-6
command (MDCMR) 26-7
control (MDCR) 26-6
data size (MDDSR) 26-11
error status (MDESR) 26-10
input FIFO (MDIF) 26-12
message data size (MDMDS) 26-12
message digest registers 0 (MDDx0) 26-12
message digest registers 1 (MDDx1) 26-13
mode (MDMR) 26-4
status (MDSR) 26-8
low-power control (LPCR) 8-3
low-power interrupt control (LPICR) 8-2
address (QAR) 23-14
command RAM (QCRn) 23-14
data (QDR) 23-14
delay (QDLYR) 23-11
interrupt (QIR) 23-12
mode (QMR) 23-9
wrap (QWR) 23-12
control (RCR) 10-2
status (RSR) 10-3
control (RNGCR) 27-1
entropy (RNGER) 27-3
output FIFO (RNGOUT) 27-4
status (RNGSR) 27-2
(IACKLPRn) 13-11
INTFRCLn) 13-9
,
1-8
MCF5271 Reference Manual, Rev. 2
SCM
SDRAM controller
SKHA
SRAM
timers
UART modules
bus master park (MPARK) 11-11
core reset status (CRSR) 11-6
core watchdog control (CWCR) 11-7
core watchdog service (CWSR) 11-8
grouped peripheral access control (GPACR) 11-17
IPSBAR 11-3
master privilege (MPR) 11-14
peripheral access control (PACRn) 11-15
RAMBAR 3-8
address and control 0–1 (DACRn) 18-6
control (DCR) 18-5
mask (DMRn) 18-9
mode register
command (SKCMR) 28-9
context (SKCRn) 28-15
control (SKCR) 28-8
data size (SKDSR) 28-13
error status (SKESR) 28-11
error status mask (SKESMR) 28-12
key data (SKKDRn) 28-14
key size (SKKSR) 28-13
mode (SKMR) 28-7
status (SKSR) 28-10
RAMBAR 6-2
DTIM
PIT
WDT
auxiliary control (UACRn) 24-13
baud rate generator (UBG1n/UBG2n) 24-15
clock select (UCSRn) 24-10
command (UCRn) 24-10
input port (UIPn) 24-16
input port change (UIPCRn) 24-13
interrupt status/mask (UISRn/UIMRn) 24-14
initialization 18-24
settings 18-19
capture (DTCRn) 22-8
counters (DTCNn) 22-8
event (DTERn) 22-6
mode (DTMRn) 22-4
reference (DTRRn) 22-7
control and status (PCSR) 21-3
count (PCNTR) 21-5
modulus (PMR) 21-5
control (WCR) 20-3
count (WCNTR) 20-4
modulus (WMR) 20-4
service (WSR) 20-4
,
11-4
Index-7