MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 256

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Interrupt Controller Modules
13-8
Address
Reset
Reset
31–0
Bits
W
W
R
R
31
15
1
1
If an interrupt source is being masked in the interrupt controller mask
register (IMR) or a module’s interrupt mask register while the
interrupt mask in the status register (SR[I]) is set to a value lower than
the interrupt’s level, a spurious interrupt may occur. This is because by
the time the status register acknowledges this interrupt, the interrupt
has been masked. A spurious interrupt is generated because the CPU
cannot determine the interrupt source. To avoid this situation for
interrupts sources with levels 1-6, first write a higher level interrupt
mask to the status register, before setting the mask in the IMR or the
module’s interrupt mask register. After the mask is set, return the
interrupt mask in the status register to its previous value. Since level 7
interrupts cannot be disabled in the status register prior to masking,
use of the IMR or module interrupt mask registers to disable level 7
interrupts is not recommended.
INT_MASK Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRH bit
Name
30
14
1
1
Figure 13-3. Interrupt Mask Register High (IMRH)
29
13
1
1
determines whether an interrupt condition can generate an interrupt. The corresponding
IPRH bit reflects the state of the interrupt signal even if the corresponding IMRH bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
28
12
1
1
Table 13-6. IMRH Field Descriptions
27
11
1
1
MCF5271 Reference Manual, Rev. 2
26
10
1
1
25
IPSBAR + 0x00_0C08
1
1
9
NOTE
INT_MASK
INT_MASK
24
1
1
8
23
Description
1
1
7
22
1
6
1
21
1
1
5
20
1
1
4
19
1
1
3
Freescale Semiconductor
18
1
1
2
17
1
1
1
16
1
1
0