MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 47

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Features
1.3.13 Software Watchdog Timer
The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog
counter is a free-running down-counter that generates a reset on underflow. To prevent a reset,
software must periodically restart the countdown.
1.3.14 Clock Module and Phase Locked Loop (PLL)
The clock module contains a crystal oscillator (OSC), phase-locked loop (PLL), reduced
frequency divider (RFD), status/control registers, and control logic. To improve noise immunity,
the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits
are powered by the normal supply pins, VDD, VSS, OVDD, and OVSS.
1.3.15 Interrupt Controllers (INTC0, INTC1)
There are two interrupt controllers on the MCF5271, each of which can support up to 63 interrupt
sources each for a total of 126. Each interrupt controller is organized as 7 levels with 9 interrupt
sources per level. Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of
a given controller provide a programmable level [1-7] and priority within the level.
1.3.16 DMA Controller
The Direct Memory Access (DMA) Controller Module provides an efficient way to move blocks
of data with minimal processor interaction. The DMA module provides four channels
(DMA0-DMA3) that allow byte, word, longword or 16-byte burst line transfers. These transfers
are triggered by software explicitly setting a DCRn[START] bit. Other sources include the DMA
timer, external sources via the DREQ signal, and UARTs. The DMA controller supports dual
address to off-chip or on-chip devices.
1.3.17 External Interface Module (EIM)
The external bus interface handles the transfer of information between the core and memory,
peripherals, or other processing elements in the external address space. Features have been added
to support external Flash modules, for secondary wait states on reads and writes, and a signal to
support Active-Low Address Valid (a signal on most Flash memories).
Programmable chip-select outputs provide signals to enable external memory and peripheral
circuits, providing all handshaking and timing signals for automatic wait-state insertion and data
bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the
starting address must be on a boundary that is a multiple of the block size. Each chip select can be
configured to provide read and write enable signals suitable for use with most popular static RAMs
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
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