MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 240

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MCF5270CAB100

Manufacturer Part Number
MCF5270CAB100
Description
MCU V2 COLDFIRE 64K SRAM 160-QFP
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Datasheets

Specifications of MCF5270CAB100

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
100MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
39
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
160-QFP
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5270CAB100
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Address
General Purpose I/O Module
12.3.1.5.7 UART/IRQ2 Pin Assignment Register (PAR_UART)
The PAR_UART register controls the functions of the UART and IRQ2 pins.
12-24
Reset
W
R
DREQ2
PAR_
Bits
7-0
15
0
Bits
15
14
14
PAR_EMDIO
0
0
PAR_EMDC
PAR_SCL
PAR_SDA
PAR_DREQ2 IRQ2 pin assignment. This bit configures the IRQ2 pin for its IRQ function or its DMA
Name
Address
U2RXD
Name
Reset
Figure 12-35. FEC/I2C Pin Assignment (PAR_FECI2C)
PAR_
13
0
Figure 12-36. UART Pin Assignment (PAR_UART)
W
R
Table 12-14. PAR_FECI2C Field Descriptions
U2TXD
Table 12-15. PAR_UART Field Descriptions
PAR_
FEC & I
I2C_SDA pins for one of their primary functions or GPIO.
PAR_EMDC
12
0
0
7
function.
0 IRQ2 pin configured for IRQ 2 function
1 IRQ2 pin configured for DMA request 2 (DREQ2) function
Note: GPIO on the IRQ2 pin is obtained by (1) writing a 0 to the PAR_DREQ2 bit and
(2) disabling the IRQ 2 function in the EPORT module.
Reserved, should be cleared.
PAR_U1RXD PAR_U1TXD
2
11
0
C pin assignment. These bit fields configure the EMDC, EMDIO, I2C_SCL, and
MCF5271 Reference Manual, Rev. 2
0
6
00
01
10
11
10
0
PAR_EMDIO
PAR_EMDC
FEC_EMDC
0
5
I2C_SCL
U2TXD
9
0
GPIO
IPSBAR + 0x10_0047
IPSBAR + 0x10_0048
0
8
0
4
PAR_EMDIO
FEC_EMDIO
PAR_U1CTS
0
I2C_SDA
7
U2RXD
Description
PAR_SCL
0
GPIO
3
Description
0
6
2
0
PAR_U1RTS
PAR_SCL
Reserved
I2C_SCL
0
5
GPIO
GPIO
PAR_SDA
0
1
0
4
U0RXD
PAR_SDA
0
Reserved
0
I2C_SDA
PAR_
GPIO
GPIO
0
Freescale Semiconductor
3
U0TXD
PAR_
0
2
U0CTS
PAR_
1
0
U0RTS
PAR_
0
0

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