MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 121

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.1.3.4
A hardware reset clears the CACR and disables the cache. The contents of the tag array are not
affected by the reset. Accordingly, the system startup code must explicitly perform a cache
invalidation by setting CACR[CINV] before the cache can be enabled.
5.1.3.5
As discussed in
line-fill buffer for providing temporary storage for the last fetched line.
With the cache enabled as defined by CACR[CENB], a cacheable fetch that misses in both the tag
memory and the line-fill buffer generates an external fetch. For data misses, the size of the external
fetch is always 16 bytes. For instruction misses, the size of the external fetch is determined by the
value contained in the 2-bit CLNF field of the CACR and the miss address.
relationship between the CLNF bits, the miss address, and the size of the external fetch.
Depending on the runtime characteristics of the application and the memory response speed,
overall performance may be increased by programming the CLNF bits to values {00, 01}.
For all cases of a line-sized fetch, the critical longword defined by bits [3:2] of the miss address is
accessed first followed by the remaining three longwords that are accessed by incrementing the
longword address in a modulo-16 fashion as shown below:
Once an external fetch has been initiated and the data is loaded into the line-fill buffer, the cache
maintains a special “most-recently-used” indicator that tracks the contents of the associated
Freescale Semiconductor
if miss address[3:2] = 00
if miss address[3:2] = 01
if miss address[3:2] = 10
if miss address[3:2] = 11
fetch sequence = {0x0, 0x4, 0x8, 0xC}
fetch sequence = {0x4, 0x8, 0xC, 0x0}
fetch sequence = {0x8, 0xC, 0x0, 0x4}
fetch sequence = {0xC, 0x0, 0x4, 0x8}
Reset
Cache Miss Fetch Algorithm/Line Fills
Section 5.1.2, “Physical
CLNF[1:0
Table 5-1. Initial Fetch Offset vs. CLNF Bits
00
01
1X
]
MCF5271 Reference Manual, Rev. 2
Line
Line
Line
00
Organization,” the cache hardware includes a 16-byte
Longword Address Bits
Line
Line
Line
01
Longword
Line
Line
10
Longword
Longword
Line
11
Table 5-1
shows the
Introduction
5-5