MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 77

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

All ColdFire processors inhibit interrupt sampling during the first instruction of all exception
handlers. This allows any handler to effectively disable interrupts, if necessary, by raising the
interrupt mask level contained in the status register. In addition, the V2 core includes a new
instruction (STLDSR) that stores the current interrupt mask level and loads a value into the SR.
This instruction is specifically intended for use as the first instruction of an interrupt service
routine which services multiple interrupt requests with different interrupt levels. For more details
see
3.6
The exception stack frame is shown in
contains the 16-bit format/vector word (F/V) and the 16-bit status register, and the second
longword contains the 32-bit program counter address.
Freescale Semiconductor
Section 3.14, “ColdFire Instruction Set Architecture
Exception Stack Frame Definition
“Fault” refers to the PC of the instruction that caused the exception; “Next” refers to the
PC of the next instruction that follows the instruction that caused the fault.
Number(s)
64–255
Vector
15–23
25–31
32–47
48–63
Table 3-7. Exception Vector Assignments (Continued)
6–7
10
12
13
14
24
11
3
4
5
8
9
0x03C–0x05C
0x080–0x0BC
0x0C0–0x0FC
0x018–0x01C
0x064–0x07C
0x100–0x3FC
Offset (Hex)
Vector
0x00C
0x02C
0x010
0x014
0x020
0x024
0x028
0x030
0x034
0x038
0x060
MCF5271 Reference Manual, Rev. 2
Figure
Program
3-5. The first longword of the exception stack frame
Stacked
Counter
Fault
Fault
Fault
Fault
Fault
Fault
Fault
Next
Next
Next
Next
Next
—
—
—
—
—
Enhancements.”
Unimplemented line-a opcode
Unimplemented line-f opcode
Trap # 0-15 instructions
User-defined interrupts
Privilege violation
Spurious interrupt
Illegal instruction
Debug interrupt
Divide by zero
Address error
Assignment
Format error
Reserved
Reserved
Reserved
Reserved
Reserved
Trace
Exception Stack Frame Definition
3-11