MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 261

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

13.2.1.6.1 Interrupt Sources
The following tables list the interrupt sources for each interrupt request line for INTC0 and
INTC1.
Freescale Semiconductor
Sourc
10
12
13
14
15
16
17
18
19
20
21
22
11
e
1
2
3
4
5
6
7
8
9
EPORT
UART0
UART1
UART2
Modul
TMR0
TMR1
TMR2
TMR3
QSPI
SCM
DMA
I
2
e
C
DONE
DONE
DONE
DONE
EPF1
EPF2
EPF3
EPF4
EPF5
EPF6
EPF7
SWTI
Table 13-13. Interrupt Source Assignment For INTC
Flag
INT
INT
INT
INT
INT
INT
INT
INT
IIF
Edge port flag 1
Edge port flag 2
Edge port flag 3
Edge port flag 4
Edge port flag 5
Edge port flag 6
Edge port flag 7
Software watchdog timeout
DMA Channel 0 transfer complete Write DONE = 1
DMA Channel 1 transfer complete Write DONE = 1
DMA Channel 2 transfer complete Write DONE = 1
DMA Channel 3 transfer complete Write DONE = 1
UART0 interrupt
UART1 interrupt
UART2 interrupt
I
QSPI interrupt
TMR0 interrupt
TMR1 interrupt
TMR2 interrupt
TMR3 interrupt
2
C interrupt
Source Description
MCF5271 Reference Manual, Rev. 2
Not used
Write EPF1 = 1
Write EPF2 = 1
Write EPF3 = 1
Write EPF4 = 1
Write EPF5 = 1
Write EPF6 = 1
Write EPF7 = 1
Cleared when service complete.
Automatically cleared
Automatically cleared
Automatically cleared
Write IIF = 0
Write 1 to appropriate QIR bit
Write 1 to appropriate TER0 bit
Write 1 to appropriate TER1 bit
Write 1 to appropriate TER2 bit
Write 1 to appropriate TER3 bit
Flag Clearing Mechanism
Memory Map/Register Definition
13-13