MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 190

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Reset Controller Module
10.2
Table 10-1
in the following paragraphs.
10.2.1 RESET
Asserting the external RESET for at least four rising CLKOUT edges causes the external reset
request to be recognized and latched.
10.2.2 RSTOUT
This active-low output signal is driven low when the internal reset controller module resets the
chip. When RSTOUT is active, the user can drive override options on the data bus.
10.3
The reset controller programming model consists of these registers:
See
10.3.1 Reset Control Register (RCR)
The RCR allows software control for requesting a reset and for independently asserting the
external RSTOUT pin.
10-2
1
2
• Reset control register (RCR), which selects reset controller functions
• Reset status register (RSR), which reflects the state of the last reset source
Table 10-2
IPSBAR Offset
S/U = supervisor or user mode access.
Writes to reserved address locations have no effect and reads return 0s.
0x11_0000
External Signal Description
Memory Map/Register Definition
provides a summary of the reset controller signal properties. The signals are described
1
RESET
RSTOUT
RESET is always synchronized except when in low-power stop mode.
for the memory map and the following paragraphs for a description of the registers.
Name
[31:24]
Table 10-1. Reset Controller Signal Properties
RCR
Table 10-2. Reset Controller Memory Map
Direction
MCF5271 Reference Manual, Rev. 2
O
I
[23:16]
RSR
Hysteresis
Input
—
Y
Reserved
[15:8]
2
Synchronization
Reserved
Input
Y
—
[7:0]
1
2
Freescale Semiconductor
Access
S/U
1