MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 273

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DSRn[DONE], shown in
When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 16, 4, or 2 when the
DMA is configured for line, longword, or word transfers, respectively, DSRn[CE] is set and no
transfer occurs. See
14.3.4.1 DMA Status Registers (DSR0–DSR3)
In response to an event, the DMA controller writes to the appropriate DSRn bit,
a write to DSRn[DONE] results in action.
Freescale Semiconductor
Bits
7
6
5
4
3
2
Name
REQ
BES
BED
Address
CE
—
—
Reset
Section 14.3.4.1, “DMA Status Registers
W
R
Reserved, should be cleared.
Configuration error. Occurs when BCR, SAR, or DAR does not match the requested
transfer size, or if BCR = 0 when the DMA receives a start condition. CE is cleared at
hardware reset or by writing a 1 to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
Bus error on source
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the read portion of a transfer.
Bus error on destination
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
Reserved, should be cleared.
Request
0 No request is pending or the channel is currently active. Cleared when the channel is
1 The DMA channel has a transfer remaining and the channel is not selected.
Figure 14-7. DMA Status Registers (DSRn)
Figure
selected.
0
0
7
Table 14-3. DSRn Field Descriptions
14-7, is set when the block transfer is complete.
CE
MCF5271 Reference Manual, Rev. 2
0
6
BES
0
5
See
BED
0
4
Figure 14-6
Description
0
0
3
REQ
(DSR0–DSR3).”
2
0
BSY
0
1
Memory Map/Register Definition
DONE
0
0
Figure
14-7. Only
14-9