MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 72

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
The following paragraphs describe the supervisor programming model registers.
3.2.3.1
The SR stores the processor status and includes the CCR, the interrupt priority mask, and other
control bits. In supervisor mode, software can access the entire SR. In user mode, only the lower
8 bits are accessible (CCR). The control bits indicate the following states for the processor: trace
mode (T bit), supervisor or user mode (S bit), and master or interrupt state (M bit). All defined bits
in the SR have read/write access when in supervisor mode.
3-6
Address
Reset
Field
10–8
Bits
7–5
4–0
15
14
13
12
11
Status Register (SR)
15
T
0
Name
CCR
—
14
0
—
—
—
M
31:24
T
S
I
13
S
0
Trace enable. When set, the processor performs a trace exception after every instruction.
Reserved, should be cleared.
Supervisor/user state. Denotes whether the processor is in supervisor mode (S = 1) or user
mode (S = 0).
Master/interrupt state. This bit is cleared by an interrupt exception, and can be set by
software during execution of the RTE or move to SR instructions.
Reserved, should be cleared.
Interrupt level mask. Defines the current interrupt level. Interrupt requests are inhibited for
all priority levels less than or equal to the current level, except the edge-sensitive level 7
request, which cannot be masked.
Reserved, should be cleared.
Refer to
Table 3-3. Supervisor Programming Model
System Byte
12
M
0
RAM Base Address Register
Table 3-4. SR Field Descriptions
Figure 3-4. Status Register (SR)
Table
Access Control Register 1
23:16
—
11
0
MCF5271 Reference Manual, Rev. 2
3-1.
10
0
0
9
I
CPU @ 0x80E
15:8
0
8
Description
0
7
—
6
0
Condition Code Register (CCR)
7:0
0
5
X
0
4
Mnemonic
RAMBAR1
ACR1
N
0
3
Freescale Semiconductor
Z
0
2
V
0
1
C
0
0