MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 313

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Data Transfer Operation
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
A[31:0], TSIZ[1:0]
R/W
TIP
TS
CSn, BSn
OE
D[31:0]
Read
Write
TA
Figure 17-11. Back-to-Back Bus Cycles
Basic read and write cycles are used to show a back-to-back cycle, but there is no restriction as to
the type of operations to be placed back to back. The initiation of a back-to-back cycle is not user
definable.
17.5.7 Burst Cycles
The MCF5271 can be programmed to initiate burst cycles if its transfer size exceeds the size of
the port it is transferring to. For example, a word transfer to an 8-bit port would take a 2-byte burst
cycle. A line transfer to a 32-bit port would take a 4-longword burst cycle.
The MCF5271 bus can support 2-1-1-1 burst cycles to maximize cache performance and optimize
DMA transfers. A user can add wait states by delaying termination of the cycle. The initiation of
a burst cycle is encoded on the size pins. For burst transfers to smaller port sizes, TSIZ[1:0]
indicates the size of the entire transfer. For example, if the MCF5271 writes a longword to an 8-bit
port, TSIZ[1:0] = 00 for the first byte transfer and does not change.
The CSCRs can be used to enable bursting for reads, writes, or both. MCF5271 memory space can
be
declared
burst-inhibited
for
reads
and
writes
by
clearing
the
appropriate
CSCRn[BSTR,BSTW]. A line access to a burst-inhibited region first accesses the MCF5271 bus
encoded as a line access. The TSIZ[1:0] encoding does not exceed the programmed port size. The
address changes if internal termination is used but does not change if external termination is used,
as shown in
Figure 17-12
and
Figure
17-13.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
17-11