MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 130

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Static RAM (SRAM)
6.2.1
The configuration information in the SRAM base address register (RAMBAR) controls the
operation of the SRAM module.
The RAMBAR contains several control fields. These fields are shown in
6-2
• The RAMBAR holds the base address of the SRAM. The MOVEC instruction provides
• The RAMBAR can be read or written from the debug module in a similar manner.
• All undefined bits in the register are reserved. These bits are ignored during writes to the
• The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other bits are
Address
Reset
Reset
31–16
15–12
write-only access to this register.
RAMBAR, and return zeroes when read from the debug module.
unaffected.
Bits
W
W
R
R
SRAM Base Address Register (RAMBAR)
Note: W for Core; R/W for Debug
—
—
31
15
0
Do not confuse this RAMBAR with the SCM RAMBAR in
Section 11.2.1.2, “Memory Base Address Register (RAMBAR).”
Although similar, this core RAMBAR enables core access to the
SRAM memory, while the SCM RAMBAR enables peripheral (e.g.
DMA and FEC) access to the SRAM.
Name
—
—
30
14
0
BA
—
Figure 6-1. SRAM Base Address Register (RAMBAR)
—
—
29
13
0
Base address. Defines the 0-modulo-64K base address of the SRAM module. By
programming this field, the SRAM may be located on any 64-Kbyte boundary within the
processor’s 4-Gbyte address space.
Reserved, should be cleared.
Table 6-1. RAMBAR Field Descriptions
—
—
28
12
0
PRI1 PRI0 SPV
—
—
27
11
MCF5271 Reference Manual, Rev. 2
—
—
26
10
25
—
—
9
NOTE
CPU + 0x0C05
WP
See Note
See Note
—
—
24
8
BA
23
—
—
Description
0
7
—
—
22
6
0
C/I
—
—
21
5
SC
—
—
20
4
Figure
SD
—
—
19
3
Freescale Semiconductor
UC
—
—
18
2
6-1.
UD
—
—
17
1
16
—
V
0
0