MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 251

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

The level and priority is fully programmable for all sources except interrupt sources 1–7. Interrupt
source 1–7 (IRQ[1:7] from the Edgeport module) are fixed at the corresponding level’s midpoint
priority. Thus, a maximum of 8 fully-programmable interrupt sources are mapped into a single
interrupt level. The “fixed” interrupt source is hardwired to the given level, and represents the
mid-point of the priority within the level. For the fully-programmable interrupt sources, the 3-bit
level and the 3-bit priority within the level are defined in the 8-bit interrupt control register (ICRx).
The operation of the interrupt controller can be broadly partitioned into three activities:
13.1.2.1 Interrupt Recognition
The interrupt controller continuously examines the request sources and the interrupt mask register
to determine if there are active requests. This is the recognition phase.
13.1.2.2 Interrupt Prioritization
As an active request is detected, it is translated into the programmed interrupt level, and the
resulting 7-bit decoded priority level (IRQ[7:1]) is driven out of the interrupt controller. The
decoded priority levels from all the interrupt controllers are logically summed together and the
highest enabled interrupt request is then encoded into a 3-bit priority level that is sent to the
processor core during this prioritization phase.
Freescale Semiconductor
• Recognition
• Prioritization
• Vector determination during IACK
Table 13-1. Interrupt Priority Within a Level
ICR[2:0]
110
101
100
011
010
001
000
111
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MCF5271 Reference Manual, Rev. 2
Fixed Midpoint Priority
7 (Highest)
0 (Lowest)
Priority
6
5
4
3
2
1
Interrupt
Sources
8–63
8–63
8–63
8–63
8–63
8–63
8–63
8–63
1–7
Introduction
13-3