MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 75

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

3.4
The original ColdFire instruction set architecture (ISA) was derived from the M68000-family
opcodes based on extensive analysis of embedded application code. After the initial ColdFire
compilers were created, developers identified ISA additions that would enhance both code density
and overall performance. Additionally, as users implemented ColdFire-based designs into a wide
range of embedded systems, they identified frequently used instruction sequences that could be
improved by the creation of new instructions. This observation was especially prevalent in
development environments that made use of substantial amounts of assembly language code.
Table 3-6
Section 3.14, “ColdFire Instruction Set Architecture
3.5
Exception processing for ColdFire processors is streamlined for performance. The ColdFire
processors differ from the M68000 family in that they include:
Freescale Semiconductor
• A simplified exception vector table
• Reduced relocation capabilities using the vector base register
• A single exception stack frame format
• Use of a single self-aligning system stack
Instruction
BYTEREV
STLDSR
Additions to the Instruction Set Architecture
BITREV
Exception Processing Overview
summarizes the new instructions added to Revision A+ ISA. For more details see
FF1
RAMBAR
Name
The contents of the destination data register are bit-reversed; that is, new Dx[31] = old Dx[0],
new Dx[30] = old Dx[1], ..., new Dx[0] = old Dx[31].
The contents of the destination data register are byte-reversed; that is, new Dx[31:24] = old
Dx[7:0], ..., new Dx[7:0] = old Dx[31:24].
The data register, Dx, is scanned, beginning from the most-significant bit (Dx[31]) and ending
with the least-significant bit (Dx[0]), searching for the first set bit. The data register is then
loaded with the offset count from bit 31 where the first set bit appears.
Pushes the contents of the status register onto the stack and then reloads the status register
with the immediate data value.
Table 3-5. ColdFire CPU Registers (Continued)
Table 3-6. ISA Revision A+ New Instructions
CPU Space (Rc)
0xC05
MCF5271 Reference Manual, Rev. 2
Local Memory Registers
Written with
MOVEC
Yes
Description
Enhancements.”
SRAM base address register
Register Name
Additions to the Instruction Set Architecture
3-9