MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 511

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

26.4.5
An NMAC consists of one Hash operation.
Freescale Semiconductor
7. MDDSR register write. Load this register with the length of the message data (without
8. MDHA does the required algorithm’s auto padding of the message.
9. Set the MDCMR[GO] bit.
10. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful
11. If MDSR[DONE] is set or done interrupt is triggered, then read the message digest from
1. Reset the MDHA using the MDCMR[SWR] bit.
2. MDCR register write. Enable the interrupts. (optional)
3. MDMR register write. Select algorithm, data padding, HMAC.
4. Direct context load of the second key into DDx1 registers from OPAD step.
5. MDMDS register write. Load this register with the length of the key.
6. Direct context load of the first key into MDx0 registers from IPAD step.
7. MDDSR register write. Load this register with the length of the message data (without
8. Direct context load of MDMDS register with key size (for NMAC load with data size of 0
9. Fill data FIFO with message to be hashed.
10. MDHA does the required algorithm’s auto padding of the message.
11. Set the MDCMR[GO] bit.
12. Wait for MDSR[INT] to be set or done interrupt to be triggered to indicate successful
padding) in bytes.
completion (or failure).
the message digest registers.
padding) in bits.
bytes).
completion (or failure).
Performing an NMAC
You will need to provide a time-out feature in your interrupt handler.
The MDHA will stall with no response if it is waiting for message
data. This will most likely occur if the MDDSR write is not received
or auto-padding is disabled and a partial message block is provided.
MCF5271 Reference Manual, Rev. 2
NOTE
Initialization/Application Information
26-19