MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 197

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Functional Description
If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus cycle to
complete (5, 6) for an external reset request, the cycle is terminated. The reset status bits are
latched (7) and reset processing waits for the external RESET pin to negate (8).
If a loss-of-clock or loss-of-lock condition is detected during the 512 cycle wait, the reset sequence
continues after a PLL lock (9, 9A).
10.4.3.2 Reset Status Flags
For a POR reset, the POR bit in the RSR are set, and the SOFT, WDR, EXT, LOC, and LOL bits
are cleared even if another type of reset condition is detected during the reset sequence for the
POR.
If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus cycle to
complete (5, 6) for an external reset request, the EXT, SOFT, and/or WDR bits along with the LOC
and/or LOL bits are set.
If the RSR bits are latched (7) during the EXT, SOFT, and/or WDR reset sequence with no other
reset conditions detected, only the EXT, SOFT, and/or WDR bits are set.
If the RSR bits are latched (4) during the internal reset sequence with the RESET pin not asserted
and no SOFT or WDR event, then the LOC and/or LOL bits are the only bits set.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
10-9