MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 284

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

DMA Controller Module
If DSIZE is another size, data writes are optimized to write the largest size allowed based on the
address, but not exceeding the configured size.
14.4.4.3 Bandwidth Control
Bandwidth control makes it possible to force the DMA off the bus to allow access to another
device. DCRn[BWC] provides seven levels of block transfer sizes. If the BCRn decrements to a
multiple of the decode of the BWC, the DMA bus request negates until the bus cycle terminates.
If a request is pending, the arbiter may then pass bus mastership to another device. If
auto-alignment is enabled, DCRn[AA] = 1, the BCRn may skip over the programmed boundary,
in which case, the DMA bus request is not negated.
If BWC = 000, the request signal remains asserted until BCRn reaches zero. DMA has priority
over the core. Note that in this scheme, the arbiter can always force the DMA to relinquish the bus.
See
14.4.5 Termination
An unsuccessful transfer can terminate for one of the following reasons:
14-20
• Error conditions—When the MCF5271 encounters a read or write cycle that terminates
• Interrupts—If DCRn[INT] is set, the DMA drives the appropriate internal interrupt signal.
Section 11.3.3, “Bus Master Park Register
with an error condition, DSRn[BES] is set for a read and DSRn[BED] is set for a write
before the transfer is halted. If the error occurred in a write cycle, data in the internal
holding register is lost.
The processor can read DSRn to determine whether the transfer terminated successfully or
with an error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE
and error bits.
MCF5271 Reference Manual, Rev. 2
(MPARK).”
Freescale Semiconductor