MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 104

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Enhanced Multiply-Accumulate Unit (EMAC)
Table 4-2
4-8
Bits
3–0
4
3
2
1
0
summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.
Name
R/T
EV
N
Z
V
Table 4-1. MACSR Field Descriptions (Continued)
Round/truncate mode. Controls the rounding procedure for MOV.L ACCx,Rx, or MSAC.L
instructions when operating in fractional mode.
0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator.
1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is
Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC,
MSAC, and load operations; it is not affected by MULS and MULU instructions.
Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC,
MSAC, and load operations; it is not affected by MULS and MULU instructions.
Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction indicating that
the result cannot be represented in the limited width of the EMAC. V is set only if a product
overflow occurs or the accumulation overflows the 48-bit structure. V is evaluated on each
MAC or MSAC operation and uses the appropriate PAVx flag in the next-state V evaluation.
Extension overflow. Signals that the last MAC or MSAC instruction overflowed the 32 lsbs
in integer mode or the 40 lsbs in fractional mode of the destination accumulator. However,
the result is still accurately represented in the combined 48-bit accumulator structure.
Although an overflow has occurred, the correct result, sign, and magnitude are contained
in the 48-bit accumulator. Subsequent MAC or MSAC operations may return the
accumulator to a valid 32/40-bit result.
Additionally, when a store accumulator instruction is executed (MOV.L ACCx,Rx), the 8
lsbs of the 48-bit accumulator logic are simply truncated.
rounded to the nearest 40-bit value. If the low-order 24 bits equal 0x80_0000, the upper
40 bits are rounded to the nearest even (lsb = 0) value. See
“Rounding.” Additionally, when a store accumulator instruction is executed (MOV.L
ACCx,Rx), the lsbs of the 48-bit accumulator logic are used to round the resulting 16- or
32-bit value. If MACSR[S/U] = 0 and MACSR[R/T] = 1, the low-order 8 bits are used to
round the resulting 32-bit fraction. If MACSR[S/U] = 1, the low-order 24 bits are used to
round the resulting 16-bit fraction.
MCF5271 Reference Manual, Rev. 2
Flags
Description
Section 4.4.1.1.1,
Freescale Semiconductor