MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 67

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chapter 3
ColdFire Core
This section describes the organization of the Version 2 (V2) ColdFire
overview of the program-visible registers. For detailed information on instructions, see the
ColdFire Family Programmer’s Reference Manual.
3.1
Figure 3-1
The processor core is comprised of two separate pipelines that are decoupled by an instruction
buffer.
The Instruction Fetch Pipeline (IFP) is a two-stage pipeline for prefetching instructions. The
prefetched instruction stream is then gated into the two-stage Operand Execution Pipeline (OEP),
Freescale Semiconductor
Processor Pipelines
is a block diagram showing the processor pipelines of a V2 ColdFire core.
Instruction
Fetch
Pipeline
Operand
Execution
Pipeline
Figure 3-1. ColdFire Processor Core Pipelines
DSOC
AGEX
IAG
IC
IB
Decode & Select,
Instruction Buffer
Operand Fetch
MCF5271 Reference Manual, Rev. 2
Generation,
Fetch Cycle
Generation
Instruction
Instruction
Address
Address
Execute
FIFO
Read Data[31:0]
Write Data[31:0]
Address [31:0]
®
processor core and an
3-1