MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 269

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Any operation involving the DMA module follows the same three steps:
14.3
This section describes each internal register and its bit assignment. Note that modifying DMA
control registers during a DMA transfer can result in undefined operation.
mapping of DMA controller registers.
Freescale Semiconductor
1
1. Channel initialization—Channel registers are loaded with control information, address
2. Data transfer—The DMA accepts requests for operand transfers and provides addressing
3. Channel termination—Occurs after the operation is finished, either successfully or due to
Located within the SCM, but listed here for clarity.
Channel
pointers, and a byte-transfer count.
and bus control for the transfers.
an error. The channel indicates the operation status in the channel’s DSR, described in
Section 14.3.4.1, “DMA Status Registers
DMA
—
0
1
2
3
Memory Map/Register Definition
Table 14-1. Memory Map for DMA Controller Module Registers
IPSBAR Offset
0x00_011C
0x00_012C
0x00_013C
0x00_0014
0x00_0100
0x00_0104
0x00_0108
0x00_0110
0x00_0114
0x00_0118
0x00_0120
0x00_0124
0x00_0128
0x00_0130
0x00_0134
0x00_0138
0x00_010C
Status Register 0
Status Register 1
Status Register 2
Status Register 3
(DSR0)
(DSR1)
(DSR2)
(DSR3)
[31:24]
MCF5271 Reference Manual, Rev. 2
DMA Request Control Register (DMAREQC)
Destination Address Register 0 (DAR0)
Destination Address Register 1 (DAR1)
Destination Address Register 2 (DAR2)
Destination Address Register 3 (DAR3)
Source Address Register 0 (SAR0)
Source Address Register 1 (SAR1)
Source Address Register 2 (SAR2)
Source Address Register 3 (SAR3)
(DSR0–DSR3).”
[23:16]
Control Register 0 (DCR0)
Control Register 1 (DCR1)
Control Register 2 (DCR2)
Control Register 3 (DCR3)
Byte Count Register 0 (BCR0)
Byte Count Register 1 (BCR1)
Byte Count Register 2 (BCR2)
Byte Count Register 3 (BCR3)
[15:8]
Memory Map/Register Definition
Table 14-1
1
[7:0]
shows the
14-5