MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 542

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

IEEE 1149.1 Test Access Port (JTAG)
29.2.2 Test Clock Input (TCLK)
The TCLK pin is a dedicated JTAG clock input to synchronize the test logic. Pulses on TCLK shift
data and instructions into the TDI pin on the rising edge and out of the TDO pin on the falling edge.
TCLK is independent of the processor clock. The TCLK pin has an internal pull-up resistor and
holding TCLK high or low for an indefinite period does not cause JTAG test logic to lose state
information.
29.2.3 Test Mode Select/Breakpoint (TMS/BKPT)
The TMS pin is the test mode select input that sequences the TAP state machine. TMS is sampled
on the rising edge of TCLK. The TMS pin has an internal pull-up resistor.
The BKPT pin is used to request an external breakpoint. Assertion of BKPT puts the processor into
a halted state after the current instruction completes.
29.2.4 Test Data Input/Development Serial Input (TDI/DSI)
The TDI pin receives serial test and data, which is sampled on the rising edge of TCLK. Register
values are shifted in least significant bit (lsb) first. The TDI pin has an internal pull-up resistor.
The DSI pin provides data input for the debug module serial communication port.
29.2.5 Test Reset/Development Serial Clock (TRST/DSCLK)
The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces
the TAP controller to the test-logic-reset state.
The DSCLK pin clocks the serial communication port to the debug module. Maximum frequency
is 1/5 the processor clock speed. At the rising edge of DSCLK, the data input on DSI is sampled
and DSO changes state.
29-4
The JTAG_EN does not support dynamic switching between JTAG
and BDM modes.
Table 29-3. Signal State to the Disable Module
Disabling JTAG
Disabling BDM
MCF5271 Reference Manual, Rev. 2
JTAG_EN = 0
TRST = 0
TMS = 1
NOTE
—
Disable DSCLK
JTAG_EN = 1
BKPT = 1
DSI = 0
—
Freescale Semiconductor