MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 58

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Signal Descriptions
2.3.2 PLL and Clock Signals
Table 2-3
2.3.3 Mode Selection
Table 2-4
2.3.4 External Memory Interface Signals
Table 2-5
2-8
Address Bus
Data Bus
External Clock In
Crystal
Clock Out
Clock Mode Selection
Reset Configuration
Signal Name
Signal Name
Signal Name
describes signals that are used to support the on-chip clock generation circuitry.
describes signals used in mode selection.
describes signals that are used for doing transactions on the external bus.
A[23:0]
D[31:0]
Abbreviation
EXTAL
XTAL
CLKOUT
Abbreviation
CLKMOD[1:0] Configure the clock mode after reset.
RCON
Abbreviation
Table 2-5. External Memory Interface Signals
Table 2-4. Mode Selection Signals
Table 2-3. PLL and Clock Signals
MCF5271 Reference Manual, Rev. 2
The 24 dedicated address signals define the address of external byte,
word, and longword accesses. These three-state outputs are the 24
lsbs of the internal 32-bit address bus and multiplexed with the
SDRAM controller row and column addresses.
These three-state bidirectional signals provide the general purpose
data path between the processor and all other devices.
The D[15:0] pins can be configured as GPIO when using a 16-bit bus.
Always driven by an external clock input except when used as a
connection to the external crystal when the internal oscillator circuit is
used. The clock source is configured during reset by CLKMOD[1:0].
Used as a connection to the external crystal when the internal
oscillator circuit is used to drive the crystal.
This output signal reflects one-half the internal system clock. (f
Indicates whether the external D[31:16] pin states affect chip
configuration at reset.
Function
Function
Function
Freescale Semiconductor
sys/2
)
I/O
I/O
I/O
I/O
O
O
O
I
I
I