MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 68

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
which decodes the instruction, fetches the required operands and then executes the required
function. Since the IFP and OEP pipelines are decoupled by an instruction buffer which serves as
a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP
thereby minimizing time stalled waiting for instructions.
The Instruction Fetch Pipeline consists of two stages with an instruction buffer stage:
When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the
Operand Execution Pipeline. If the buffer is not empty, the IFP stores the contents of the fetch
cycle in the FIFO queue until it is required by the OEP. In the Version 2 implementation, the
instruction buffer contains three 32-bit longwords of storage.
The Operand Execution Pipeline is implemented in a two-stage pipeline featuring a traditional
RISC datapath with a dual-read-ported register file (RGF) feeding an arithmetic/logic unit. In this
design, the pipeline stages have multiple functions:
3.2
The following paragraphs describe the processor registers in the user and supervisor programming
models. The appropriate programming model is selected based on the privilege level (user mode
or supervisor mode) of the processor as defined by the S bit of the status register (SR).
3.2.1
Figure 3-2
microprocessors, consisting of the following registers:
3.2.1.1
Registers D0–D7 are used as data registers for bit (1-bit), byte (8-bit), word (16-bit) and longword
(32-bit) operations; they can also be used as index registers.
3-2
• Instruction Address Generation (IAG Cycle)
• Instruction Fetch Cycle (IC Cycle)
• Instruction Buffer (IB Cycle)
• Decode & Select/Operand Cycle (DSOC Cycle)
• Address Generation/Execute Cycle (AGEX Cycle)
• 16 general-purpose 32-bit registers (D0–D7, A0–A7)
• 32-bit program counter (PC)
• 8-bit condition code register (CCR)
Processor Register Description
User Programming Model
illustrates the user programming model. The model is the same as the M68000 family
Data Registers (D0–D7)
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor