MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 74

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
3.2.3.5
The access control registers, ACR0 and ACR1, define attributes for two user-defined memory
regions. These attributes include the definition of cache mode, write protect, and buffer write
enables. The ACRs are described in
3.2.3.6
The RAMBAR register is used to specify the base address of the internal SRAM and indicate the
types of references mapped to it. The base address register includes a base address, write-protect
bit, address space mask bits, and an enable bit. For more information, refer to
“SRAM Base Address Register
3.3
Table 3-5
processor using the MOVEC instruction.
3-8
Memory Map/Register Definition
lists register names, the CPU space location, and whether the register is written from the
Access Control Registers (ACR0, ACR1)
SRAM Base Address Register (RAMBAR)
ACR0, ACR1
ACC0–ACC3
OTHER_A7
ACCext01
ACCext23
MACSR
D0–D7
A0–A7
CACR
MASK
Name
VBR
SR
PC
0x(0,1)88–0x(0,1)8F
0x(0,1)80–0x(0,1)87
CPU Space (Rc)
0x806, 0x809,
0x80A, 0x80B
0x004–0x005
Table 3-5. ColdFire CPU Registers
0x80E
0x002
0x800
0x801
0x804
0x805
0x807
0x808
0x80F
(RAMBAR)”.
Memory Management Control Registers
Processor General-Purpose Registers
Processor Miscellaneous Registers
MCF5271 Reference Manual, Rev. 2
Section 5.2.1.2, “Access Control Registers (ACR0,
Written with
MOVEC
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
Cache control register
Access control registers 0 and 1
Data registers 0-7 (0 = load, 1 = store)
Address registers 0-7 (0 = load, 1 = store)
A7 is user stack pointer
Other stack pointer
Vector base register
MAC status register
MAC address mask register
MAC accumulators 0-3
MAC accumulator 0, 1 extension bytes
MAC accumulator 2, 3 extension bytes
Status register
Program counter
Register Name
Freescale Semiconductor
Section 6.2.1,
ACR1).”