MCF5270CAB100 Freescale Semiconductor, MCF5270CAB100 Datasheet - Page 348

• Manufacturer Part Number: MCF5270CAB100
• Description: MCU V2 COLDFIRE 64K SRAM 160-QFP
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270CAB100

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-QFP
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Fast Ethernet Controller (FEC)
19.1.4 Modes of Operation
The primary operational modes are described in this section.
19.1.4.1 Full and Half Duplex Operation
Full duplex mode is intended for use on point to point links between switches or end node to
switch. Half duplex mode is used in connections between an end node and a repeater or between
repeaters. Selection of the duplex mode is controlled by TCR[FDEN].
When configured for full duplex mode, flow control may be enabled. Refer to the
TCR[RFC_PAUSE] and TCR[TFC_PAUSE] bits, the RCR[FCE] bit, and
Duplex Flow
19.1.5 Interface Options
The following interface options are supported. A detailed discussion of the interface
configurations is provided in
19.1.5.1 10 Mbps and 100 Mbps MII Interface
MII is the Media Independent Interface defined by the IEEE 802.3 standard for 10/100 Mbps
operation. The MAC-PHY interface may be configured to operate in MII mode by asserting
RCR[MII_MODE].
The speed of operation is determined by the ETXCLK and ERXCLK pins which are driven by the
external transceiver. The transceiver will either auto-negotiate the speed or it may be controlled by
19-4
• Support for full-duplex operation (200Mbps throughput) with a minimum system clock rate
• Support for half-duplex operation (100Mbps throughput) with a minimum system clock
• Retransmission from transmit FIFO following a collision (no processor bus utilization)
• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
• Address recognition
of 50 MHz
rate of 25 MHz
recognition rejects (no processor bus utilization)
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
Control,” for more details.
Section 19.3.5, “Network Interface
MCF5271 Reference Manual, Rev. 2
Options”.
Section 19.3.10, “ Full
Freescale Semiconductor