pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 98

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Number
INT11
INT12
INT13
INT14
INT15
INT16
INT17
INT18
INT19
INT20
INT21
INT22
INT23
INT24
INT25
INT26
INT27
INT28
INT29
INT30
INT31
1. To enable the external interrupt, set the pin to its alternate function. When used as I/O port signals the External
2. When in Active mode, it is advised to disable the T0OUT channel of the MIWU, this saves the need to clear the
3. Falling Edge is enabled for this input when the PS/2 channel ‘Disabled Shift Mechanism Interrupts’ are enabled
INT
interrupt input is forced to 0
pending bit in the MIWU on each interrupt.
(DSMIE in PSIEN register = 1).
External/MIWU
External/MIWU
External/MIWU
External/MIWU
Internal/MIWU
Internal/MIWU
Reserved
Reserved
Source
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
MIWU
Edge Falling
Edge Falling
Edge Falling
Edge Rising
Level High /
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Level-High
Table 15. ICU Interrupt Assignments (Continued)
Type
3
Internal Keyboard Scan Interrupt (KBSINT from MIWU) or
ACM Interrupt
MSWC interrupt through the MIWU
TWM system tick (T0OUT), through the MIWU
SWIN input
USART1 Interrupt (TX Int OR RX int)
External Interrupt EXWINT24 through the MIWU
PS/2 shift mechanism (PSINT3)
PS/2 shift mechanism (PSINT2)
PS/2 shift mechanism (PSINT1)
External Interrupt EXWINT22 through the MIWU
MFT16 2 Interrupt (INT1 ORed with INT2)
Shared Memory Interrupt
Host I/F Keyboard/Mouse channel Input Buffer Full
Host I/F Power Management channel 1 or channel 2 Input
Buffer Full
DMA Channel 0 (USART1 Rx DMA)
DMA Channel 1 (USART1 Tx DMA) or USART2 Interrupt
(Tx Int or Rx int)
DMA Channel 2 (ACCESS.bus 3 DMA)
DMA Channel 3 (ACCESS.bus 4 DMA)
External Interrupt EXWINT21 through the MIWU
(Continued)
1
98
, through the MIWU
Details
2
1
1
1
Priority
Highest
Revision 1.2