pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 188

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Master Stop
To end a transaction, set STOP in ACBnCTL1 register before clearing the current stall flag (i.e., SDAST, NEGACK or STAS-
TR in ACBnST register). This causes the module to send a Stop Condition immediately and to clear STOP in ACBnCTL1
register. A Stop Condition may be issued only when the PC87591L-N05 is the active bus master (MASTER in ACBnST reg-
ister is set to 1).
Master Bus Stall
The ACB module can stall the ACCESS.bus between transfers while waiting for the core’s or DMA’s response. The AC-
CESS.bus is stalled by holding the SCLn signal low after the acknowledge cycle. Note that this is interpreted as the start of
the following bus operation. The user must make sure that the next operation is prepared before the flag that causes the bus
stall is cleared.
The flags that can cause a bus stall in Master mode are:
Repeated Start
A repeated start is performed when the PC87591L-N05 is already the bus master (MASTER in ACBnST register is set). In this
case, the ACCESS.bus is stalled and the ACB module awaits core handling due to a negative acknowledge (NEGACK in ACBnST
register is set to 1), an empty buffer (SDAST in ACBnST is set to 1) and/or a stall after start (STASTR in ACBnST is set to 1).
For a repeated start:
1. Set START in ACBnCTL1 register to 1.
2. In Master Receive mode, read the last data item from ACBnSDA.
3. Follow the address send sequence, as described in “Sending the Address Byte” on page 187.
4. If the ACB is awaiting handling because STASTR in ACBnST is set to 1, clear it only after writing the requested address
Master Error Detection
The ACB detects an illegal Start or Stop Condition (i.e., a Start or Stop Condition within the data transfer or the acknowledge
cycle) and a conflict on the data lines of the ACCESS.bus. If an illegal condition is detected, BER is set and Master mode is
exited (MASTER in ACBnST register is cleared).
Bus Idle Error Recovery
When a request to become the active bus master or a restart operation fails, BER in ACBnST register is set to indicate the
error. In some cases, both the PC87591L-N05 and the other device may identify the failure and leave the bus idle. In this
case, the start sequence may not finish and the ACCESS.bus may remain deadlocked.
To recover from deadlock, use the following sequence:
1. Clear BER in ACBnST register and BB in ACBnCST register.
2. Wait for a time-out period to check that there is no other active master on the bus (i.e., BB in ACBnCST remains cleared).
3. Disable and then re-enable the ACB to put it in non-addressed Slave mode. (This completely resets the module.)
At this point, some of the slaves may not identify the bus error. To recover, the ACB module becomes the bus master. It
asserts a Start Condition, sends an address byte and then asserts a Stop Condition that synchronizes all the slaves.
4.13.4 Slave Mode
A slave device waits in Idle mode for a master to initiate a bus transaction. Whenever the ACB module is enabled is not
acting as a master (i.e., MASTER in ACBnST register is cleared), it acts as a slave device.
Once a Start Condition on the bus is detected, the PC87591L-N05 checks whether the address sent by the current master
matches any of the following possibilities:
The address match is checked even when MASTER in ACBnST register is set. If a bus conflict (on SDAn or SCLn) is de-
tected, BER is set, MASTER is cleared and the PC87591L-N05 continues to search the received message for a match.
• Negative acknowledge after sending a byte (NEGACK in ACBnST register is set to 1).
• SDAST in ACBnST register is set to 1.
• STASTRE in ACBnCTL1 register is set to 1 after a successful start (STASTR in ACBnST is set to 1).
• The ADDR value in ACBnADDR register, if SAEN in this register is set to 1
• The ADDR value in ACBnADDR2 register, if SAEN in this register is set to 1
• The global call address (00
• The global ARP address (110 0001
and direction to ACBnSDA.
16
), if GCMEM in ACBnCTL1 register is set to 1
2
), if ARPMEN in ACBnCTL3 register is set to 1.
(Continued)
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Revision 1.2