pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 270

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Module
Shared Memory Host Access Protect Register 1 and 2 (SMHAP1-2)
This register holds the read/write protection and lock control from the host side to the shared memory. The memory is par-
titioned into 64 Kbyte blocks. SMHAP1 controls the first 16 blocks (addresses 0-1 Mbyte). SMHAP2 controls the second
group of 16 blocks (addresses 1-2 Mbyte). The block mapping is in the core address space. See “Setting the Host Access
Protection Flags” on page 266 for the calculation method of the block address in the host address space. On Host Domain
Hardware reset, all write-protect flags are set and all lock-protect and read-protect flags are cleared.
Location: Offset 07
Type:
Shared Memory Host Semaphore Register (SMHSEM)
This register provides eight semaphore bits between the core and host. Four of the bits may be set by the host and four may
be set by the core. The register is cleared (00
Location: Offset 0C
Type:
Bit
Name
Reset
Bit
Name
Reset
7-4
Bit
3-0
7-4
Bit
0
1
2
3
Type
Type
R/W HSEM3-0. Four bits that may be updated by the host and read by both the host and the core.
R/W
R/W
R/W
R/W
RO
Varies per bit
Varies per bit
WO
CSEM3-0. Four bits that may be updated by the core and read by both the host and the core.
Host Read Protection. The block number is as held in the index field (bits 7-4). Note that the Core
Override protection may disable reads even when reads are allowed by this register.
0: Host Reads are allowed for this block (default)
1: Host Reads are inhibited for this block
Host Write Protection. The block number is as held in the index field (bits 7-4). Note that the Core
Override protection may disable writes even when writes are allowed by this register.
0: Program and erase are allowed for this block
1: Program and erase of the expansion memory are inhibited for this block (default)
Host Lock Protection. The block number is as held in the index field (bits 7-4). When set, the bit
prevents changing the values of the Host Read Protect, Host Write Protect and Host Lock Protection
bits for this block. Once set, this bit is cleared by Host Domain Hardware reset only.
0: Changes to protection bits (0-2) for this block are enabled (default)
1: Protection bits (0-2) for this block are locked, and the bits’ values may not be changed
Index Write. Indicates that this is an index write transaction; therefore, bits 0-2 of this register are
ignored. When read, always returns 0.
0: Write transaction affects all fields of this register (writes to bits 0-2 use the newly written index) (default)
1: Write transaction for purpose of index update; bits 0-2 should not be updated by this write.
Host Access Protection Index. Holds the index number of the host block accessed by the other fields
in this register. All blocks are 64 Kbytes. The block index is calculated in the core address space. For
details of the address conversion, see Section 5.3.2 on page 262.
Index = Block_First_Address / 64K
In SMHAP1: 0000-1111
In SMHAP2: 0000-1111
CSEM3
7
0
16
16
7
0
and 08
Host Access Protection Index
16
CSEM2
6
0
6
0
16
16
for indexes 16-31, respectively
for indexes 0-15, respectively
CSEM1
16
5
0
) on Host Domain Hardware reset.
5
0
(Continued)
CSEM0
270
0
4
4
0
Description
Description
Index Write
HSEM3
3
0
3
0
Host Lock
Protection
HSEM2
2
0
2
0
Host Write
Protection
HSEM1
1
1
1
0
Host Read
Protection
HSEM0
0
0
0
0
Revision 1.2