pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 228

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
The data present at the parallel output of the IR is latched from the shift register stage on the falling edge of TCK in Update-IR state.
After entry into TAP-Reset state as a result of TAP controller clocked operation, the BYPASS instruction is latched onto the
IR output on the falling edge of TCK.
Instructions
Instructions are entered serially into the Debugger interface logic during an IR scan by using the IR. See Table 29 for the
required binary codes.
Notes:
Data registers not selected by the current instruction do not interfere with the operation of the on-chip system logic or with
the selected data registers.
Each instruction enables a single serial data register path to shift data between TDI and TDO in Shift-DR state, as shown in
Table 30.
Instruction codes that are not required to control test logic are equivalent to the BYPASS instruction.
BYPASS
The BYPASS instruction operates the BYPASS register. This register contains a single shift register stage and provides a min-
imum-length serial path between the TDI and TDO pins of a component when no test operation is needed for that component.
This allows more rapid movement of test data to and from other board components that are required to perform test operations.
The BYPASS instruction selects BYPASS register to be connected for serial access between TDI and TDO in the Shift_DR state.
If the BYPASS instruction is selected, all other data registers continue their normal functionality.
Debugger Interface Instructions
SCAN_RX
The SCAN_RX instruction switches the data scan path to DBGDATA register. The DBGDATA length is set to L0 to L4; see
“Debug Data Register (DBGDATA)” on page 230. The result of the Capture-DR state of the TAP controller is unpredictable.
A parallel load of data from DBGDATA register to the DBGRXD Rx data buffer is done in Update-DR state.
The controller sets the RX_BUSY indication in DBGRXST register to 1 in Update-DR state. The PID and message fields of
the SCAN_RX instruction are available for read access, through the peripheral bus, from DBGRXST register. The ISE inter-
rupt control block asserts the ISE interrupt and RX_i bit in DBGISESRC register, according to the PID index.
DEBUGGER ABORT
This operation has no dedicated operation code. It is performed using the SCAN_RX instruction with the PID field is ‘1111’.
Following SCAN_RX mode, the ISE interrupt control block asserts ISE interrupts, together with ABORT_i bits in
DBGISESRC register, according to the MASKS values in DBGMASKS register. The assertion is triggered during the TCK
rising edge during Update-IR state. In this case, there is no RX_BUSY indication and no change in the contents of DB-
GRXST register (i.e., this format of SCAN_RX may be issued with a busy Rx data link).
• D0 is the nearest to the serial output.
• “X” means ignore.
• Debugger abort is generated by SCAN_RX when PID=‘1111’.
D11 D10 D9 D8 D7
L4
x
x
x
x
x
x
L3
x
x
x
x
x
x
All other states
L2
Controller State
x
x
x
x
x
x
L1
x
x
x
x
x
x
L0
x
x
x
x
x
x
other
PID3 PID2 PID1 PID0
D6
x
x
x
x
x
x
Undefined
D5
x
x
x
x
x
x
Table 29. IR Instruction Binary Codes
Shift Register Stage
D4
x
x
x
x
x
x
(Continued)
D3
x
x
x
x
x
x
D2 D1 D0
1
0
1
0
0
0
1
1
228
1
0
1
0
1
0
0
1
1 BYPASS
0 BYPASS (Reserved for Scan)
0 BYPASS
1 BYPASS
0 SCAN_RX
1 SCAN_TX
1 SCAN_ABORT_MASK
0 ASSERT_DBG_RST
Retain last state
Parallel Output
Instruction
Revision 1.2