pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 210

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Exit from Power Off
When in Power Off, activity can be resumed only by switching to Active mode. This is done by applying V
PC87591L-N05. The Power-Up reset sequence described in “VCC Power-Up Reset” on page 62 should be applied.
Power Mode Switch Protection
The PMC module includes a mechanism that protects the PC87591L-N05 from malfunctions caused by missing or unstable
clock signals.
Clock Toggling Indication
OHFC and OLFC bits in PMCSR register indicate the current status of the high- and low-frequency clock inputs, respectively.
The current status is based on indications from the HFCG and LFCG modules.
The PMC does not use the high-frequency clock when the OHFC bit is 0; it does not use the low-frequency clock when OLFC is 0.
During reset, the PC87591L-N05 clock does not toggle until OHFC is 1. During power mode change, if there is a request to
switch to a non-stable or non-toggling clock, the power mode change stalls.
4.17.4 The Power Management Controller Status Register (PMCSR)
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
PMCSR is a byte-wide, read/write register that selects the Active or Idle modes. In addition, it controls the operation of the
HFCG by enabling or disabling the high-frequency core clock domain. On reset, all non-reserved bits are cleared. PMCSR
format is shown below.
Location: 00 FF80
Type:
Bit
Name
Reset
4-3
Bit
0
1
2
5
6
7
Reserved.
DHF (Disable High-Frequency Oscillator). When cleared (0), the HFCG is enabled. In Active mode, the
HFCG is enabled regardless of the DHF value.
If in Idle mode, DHF can be used to reduce power consumption. When DHF=1, the HFCG is disabled and the
high-frequency clock is not generated. In Power off mode, the HFCG is disabled regardless of the DHF value.
DHF is cleared by the hardware when a hardware wake-up event is detected.
IDLE. When set, the core domain enters Idle mode on the execution of a WAIT instruction. WBPSM must be
set before executing the WAIT instruction.
This bit can be set and cleared by software; it is cleared by hardware when a hardware wake-up event is detected.
Reserved.
WBPSM (Wait Before Entering Power Save Mode). When set, the switch from Active to Idle mode is done by
setting the IDLE bit and executing a WAIT instruction. In addition, if DHF is set, the high-frequency oscillator is
disabled only after the WAIT instruction is executed and Idle mode is entered.
OHFC (Oscillating High-Frequency Clock).
0: Indicates that the high-frequency clock received by the PMC is either disabled, not available or not producing
1: Indicates that the high-frequency clock received by the PMC is available and producing a stable clock.
OLFC (Oscillating Low-Frequency Clock).
0: Indicates that the low-frequency clock received by the PMC is either disabled, not available or not producing a stable
1: Indicates that the low-frequency clock received by the PMC is available and producing a stable clock.
R/W
a stable clock. When OHFC is cleared, the PMC does not switch to Active mode (default).
clock. When the OLFC is cleared, the PMC does not switch from Active mode to Power Save or Idle modes (default).
OLFC
16
7
0
OHFC
6
0
WBPSM
5
0
(Continued)
Description
210
4
0
Reserved
3
0
IDLE
2
0
DHF
1
0
CC
power to the
Reserved
0
0
Revision 1.2