pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 8

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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Table of Contents
4.2
4.3
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10
4.1.11
DMA CONTROLLER (DMAC) ................................................................................................... 85
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
INTERRUPT CONTROL UNIT (ICU) ......................................................................................... 96
4.3.1
Clock Cycles ................................................................................................................ 69
Early Write Bus Cycle .................................................................................................. 70
Late Write Bus Cycle ................................................................................................... 73
Normal Read Bus Cycle .............................................................................................. 74
Fast Read Bus Cycle ................................................................................................... 78
I/O Expansion Bus Cycles ........................................................................................... 78
Development Support .................................................................................................. 80
BIU Registers .............................................................................................................. 81
Usage Hints ................................................................................................................. 84
Features ...................................................................................................................... 85
Functional Description ................................................................................................. 85
Channel Assignment in PC87591L-N05 ...................................................................... 86
Transfer Types ............................................................................................................ 86
Bus Policy .................................................................................................................... 88
Operation Modes ......................................................................................................... 89
Software DMA Request ............................................................................................... 90
DMAC Registers .......................................................................................................... 90
Usage Hints ................................................................................................................. 95
Features ...................................................................................................................... 96
(Continued)
Static Memory and I/O Support .............................................................................. 67
Byte Access ............................................................................................................ 67
Clock and Bus Cycles ............................................................................................ 68
Optional Clock Cycles ............................................................................................ 69
Other Clock Cycles ................................................................................................. 69
Control Signals ....................................................................................................... 70
Bus Status Signals ................................................................................................. 80
Core Bus Monitoring ............................................................................................... 80
BIU Configuration Register (BCFG) ....................................................................... 81
I/O Zone Configuration Register (IOCFG) .............................................................. 82
Static Zone Configuration Register (SZCFGn) ....................................................... 83
Direct (Fly-By) Transfers ........................................................................................ 86
Indirect (Memory-to-Memory) Transfers ................................................................. 87
Intermittent Operation Mode ................................................................................... 88
Continuous Operation Mode .................................................................................. 88
Single Transfer Operation ...................................................................................... 89
Double Buffer Operation ......................................................................................... 89
Auto-Initialize Operation ......................................................................................... 90
DMAC Register Map .............................................................................................. 90
Device A Address Counter Register (ADCAn) ....................................................... 91
Device A Address Register (ADRAn) ..................................................................... 91
Device B Address Counter Register (ADCBn) ....................................................... 91
Device B Address Register (ADRBn) ..................................................................... 91
Block Length Counter Register (BLTCn) ................................................................ 92
Block Length Register (BLTRn) .............................................................................. 92
DMA Control Register (DMACNTLn) ...................................................................... 92
DMA Status Register (DMASTATn) ....................................................................... 94
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Revision 1.2