pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 227

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
When TMS is equal to 1 for five consecutive TCK cycles, this forces the controller into TAP-Reset state from any state.
4.19.5 TAP Instruction Register
The Instruction Register (IR) allows an instruction to be shifted into the Debugger interface. The instruction selects the mode
of operation, the data register to be addressed or both.
In any serial scan operation, the JTAG serial bus controller transmits and receive vectors of the same length. This serial scan chain
property is used to transmit status bits from the device to the bus controller in any instruction scan operation. The Instruction reg-
ister in the PC87591L-N05 allows status information generated within the data links to be examined as shown in Table 28 on
page 227.
Design and Construction
The IR uses a shift register-based design with a parallel input for register cells other than the two nearest to the serial output.
An instruction, shifted into the register, is latched at the completion of the shifting process.
The IR includes 12 shift register-based cells capable of holding instruction data.
An instruction that is shifted into the register is latched so that the related changes occur only in the Update IR and TAP-
Reset states.
Data is not inverted between the serial input and serial output of IR.
The IR parallel input status bits, loaded at the Capture IR state of any instruction scan operation, are shown below.
Instruction Register Operation
Table 28 shows the behavior of IR in each TAP controller state.
All actions resulting from an instruction terminate when a new instruction is transferred to the parallel output of the IR (i.e.,
in Update-IR or TAP-Reset states).
All operations of the shift register stages occur on the rising edge of TCK after entry into a TAP controller state.
Bit
Name
Reset
11-7 MSG_LEN (Message Length). Contains the Tx message length in words. When the Tx status word PID field is
6-3
Bit
0
1
2
Fixed value (1).
Fixed value (0).
RX_BUSY (Receive Busy). Busy indication from the Rx data link.
PID (Processor ID). Contains the processor ID from the Tx data link.
When TINT is set to 1 (not active), PID field is ‘1111’, indicating that the Tx link has no valid data.
When TINT is set to 0 (active), PID field indicates the value of PID field in DBGTXLOC register. Note that this
value is latched when TINT becomes active and is held until the Rx data is read by the host.
not ‘1111’, the MSG_LEN holds a copy of the MSG_LEN field in DBGTXST register. When the size of this field
is less than five bits, the MSG_LEN MSBs in the status word are forced to 0.
TAP-Reset
Capture-IR
Shift-IR
Exit1-IR
Exit2-IR
Pause-IR
Update-IR
Controller State
11
MSG_LEN
Table 28. Instruction Register Operation in Each Controller State
7
Undefined
Load status data (table 2-2)
Shift towards serial output
Retain last state
Retain last state
6
Shift Register Stage
(Continued)
5
PID
Description
227
5
Set to give BYPASS instruction
Retain last state
Retain last state
Retain last state
Load from shift register stage
3
Parallel Output
RX_BUSY
2
1
0
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