pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 231

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
The ABORT_MASK register consists of shift register stages with 16 bits. Bits 1 to 15 are reserved and should be written with
0. A bit value of 1 enables the processor to abort; a bit value of 0 disables it.
4.19.7 Core Registers, Debugger Interface
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
Core Register Map
Debug Receive Data Registers 0, 2, 4, 6, 8, 10, 12 and 14 (DBGRXD0-14)
DBGRXD0 to DBGRXD14 is a group of eight word-wide read-only registers. The DBGRXD0-14 registers are written from
the JTAG serial bus. They can only be read from the peripheral bus. A representative DBGRXDi register is shown below.
Location: Channel 0 - 00 FDC0
Type:
Bit
Name
15-0 Receive Data (RX_DATA). Data bits 16*i through 16*i+15 of the Rx data link data buffer.
Bit
DBGRXD0-14
DBGRXST
DBGTXD0-14
DBGTXLOC
DBGTXST
DBGTINT
DBGABORT
DBGISESRCA
Channel 2 - 00 FDC2
Channel 4 - 00 FDC4
Channel 6 - 00 FDC6
Channel 8 - 00 FDC8
Channel 10 - 00 FDCA
Channel 12 - 00 FDCC
Channel 14 - 00 FDCE
RO
Mnemonic
15
14
Figure 82. ABORT_MASK and DBGMASKS Register Interaction
Debug Receive Data Registers 0, 2, 4, 6, 8, 10, 12 and 14
Debug Receive Status Register
Debug Transmit Data Registers 0, 2, 4, 6, 8, 10, 12 and 14
Debug Transmit Lock Register
Debug Transmit Status Register
Debug TINT Assert Register
Debug Abort Generate Register
Debug ISE Source Register A
13
16
16
16
16
16
16
16
16
12
TDI
11
10
(Continued)
15
15
ABORT_MASK
Register Name
DBGMASKS
9
Description
231
RX_DATAi
8
0
0
7
TDO
6
5
4
3
Varies per bit
Type
R/W
R/W
R/W
R/W
WO
WO
RO
2
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