pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 170

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Where:
See Section 7.4 on page 340 for the value of t
Input Selection Field. Each Voltage Channel has its own programmable, input selection field (SELIN in VCHNxCTL regis-
ter). This field determines which input is measured by the channel during the current ADC cycle. The field also indicates to
which input the data in the channel buffer belongs. This field may be modified after the channel buffer has been read and
the DATVAL bit has been reset.
If the input selection field is not changed, the same input is measured during the next ADC cycle. This gives a sampling rate
of one T
each input, but the period for all scanned inputs is shorter.
Operation Sequence. After the ADC is properly initialized and enabled, one of the following example sequences can be used:
EOCEV-Driven ADC Operation Sequence for All Channels
1. When End-of-Cycle is reached (i.e., after all enabled channel conversions are completed), software can detect the event
2. Read the number of input measured in Voltage Channel 1 by reading SELIN in VCHN1CTL register.
3. Read the input voltage value measured in Voltage Channel 1 by reading VCHDAT in VCHN1DAT register.
4. In preparation for the next measurement (i.e., to define which input will be measured by Voltage Channel 1 during the next
5. For Voltage Channel 2, repeat steps 5 through 7 for the VCHN2CTL and VCHN2DAT registers.
6. For Voltage Channel 3, repeat steps 5 through 7 for the VCHN3CTL and VCHN3DAT registers.
DATVAL-Driven ADC Operation Sequence for One Channel
1. Wait for the end of channel by waiting for DATVAL in VCHNxCTL register to be set to 1.
2. Read the input number by reading SELIN in VCHNxCTL register.
3. Read the measured data by reading VCHDAT in VCHNxDAT register.
4. Optional: Change the input to be measured during the next ADC cycle: in VCHNxCTL register, write a new SELIN value.
5. Prepare the voltage channel to receive new data: in VCHNxCTL register, write 1 to DATVAL to clear it.
6. In preparation for the next measurement (i.e., to define which input will be measured by the voltage channel during the
Reading Measurement Results
Polling-Driven Operation. Measurement results may be read by polling either EOCEV in ADCSTS register or each of the
three DATVAL bits in VCHNxCTL registers.
Polling EOCEV uses the sequence listed in EOCEV-Driven ADC Operation Sequence for All Channels, above. When
EOCEV is set, all three channels contain valid data and may be read.
Polling DATVAL uses the sequence listed in DATVAL-Driven ADC Operation Sequence for One Channel, above. When a
DATVAL bit is set, only its channel contains valid data that may be read. In this case, the EOCEV bit is redundant.
Interrupt-Driven Operation. The ADC may generate an interrupt to the core when any of the valid bits is set (EOCEV in
ADCSTS register or DATVAL in any VCHNxCTL register). The interrupt is generated when the interrupt enable bit for the
respective status bit is set. The software in the interrupt routine should check the status bits as described above for polling-
driven operation to verify which of the DATVAL bits is set.
An interrupt is expected from EOCEV when using the sequence listed in the EOCEV-driven ADC operation sequence (see
above). The EOCEV interrupt indicates that all three channels contain valid data and may be read. Interrupts from the
DATVAL bits should be disabled.
An interrupt is expected from one of the DATVAL bits when using the sequence listed in the DATVAL-driven ADC operation
sequence (see above). The DATVAL interrupt indicates that only its channel contains valid data that may be read. Interrupts
from the EOCEV bit should be disabled.
Failure Detection
Overflow. An overflow occurs when DATVAL bit is set at the end of a measurement, indicating that the result of the previous
measurement was not read. If an overflow occurs in at least one channel, the new measurement result overrides the old
data in the buffer, and OVFEV in ADCSTS register is set. This indicates that the result of the previous measurement was lost.
• EOCEV-driven ADC operation sequence for all voltage channels
• DATVAL-driven ADC operation sequence for one voltage channel
by waiting for EOCEV bit in ADCSTS register to be set to 1.
ADC cycle), clear DATVAL bit in VCHN1CTL register by writing 1 to it (it may be the same input or, optionally, a different one).
next ADC cycle), clear the DATVAL bit by writing 1 to it (it may be the same input or, optionally, a different one).
t
t
VD
VC
ADC cycle
- Voltage Conversion Delay Time
- Voltage Conversion time
for the specific input. If this field is changed and a different input is sampled, the sampling rate is lower for
VC
and Section Section 4.11.3 on page 167 for t
(Continued)
170
VC
calculation.
Revision 1.2