pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 229

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
SCAN_TX
The SCAN_TX instruction switches the data scan path to DBGDATA register. In Capture-DR state, DBGDATA register cap-
tures the values from the Tx data buffer DBGTXD. No parallel load is performed in Update-DR state. The length of
DBGDATA register is set to the value of MSG_LEN in DBGTXST register (see “Debug Data Register (DBGDATA)” on
page 230). No parallel load is performed in Update-DR state.
The Controller sets DBGTXLOC to all 1s and releases TINT on Update-DR state. This operation clears the semaphore and
enables the data link for a new transaction. TINT is asserted, as described in “Tx Data Link” on page 222.
SCAN_ABORT_MASK
The SCAN_ABORT_MASK instruction switches the data scan path to ABORT_MASK register. In Capture-DR state, a par-
allel update of the shift register occurs with the DBGMASKS values. Parallel load is performed in Update-DR state to update
the DBGMASKS values.
ASSERT_DBG_RST
A Debugger reset is asserted in Update-DR state. Serial data is switched to the BYPASS register.
4.19.6 TAP Data Registers, Debugger Interface
Bit Arrangement and Mapping
Figure 80 shows the bit allocation for a parallel load operation between any pair of serial shift registers and a peripheral bus
addressable register.
Functionality in Various TAP Controller States
When data is shifted through a data register, data applied to TDI appears without inversion at TDO following an appropriate
number of TCK transitions, when the TAP controller is in Shift-DR state.
The data register connected between TDI and TDO shifts data one stage towards TDO after each rising edge of TCK in
Shift-DR state.
In TAP-Reset state, all data registers either perform their system function (if one exists) or do not interfere with the operation
of the on-chip system logic.
If, in response to the current instruction, a data register loads data from a parallel input, the data is loaded on the rising edge
of TCK following entry into Capture-DR state.
If the data register connected between TDI and TDO in response to the current instruction is provided with latched parallel
data outputs, the data is latched into the parallel output buffers on the falling edge of TCK, during Update-DR or Run-
Test/Idle states, as appropriate.
If, in response to a current instruction, no operation of a selected data register is required in a given controller state, the
register retains its last state unchanged.
When the TAP controller state machine is in TAP-Reset state during Power-Up reset, IR register is reset.
Data registers that are not selected by the current instruction are set to perform their functions, as described in Section 4.19;
specifically, see “Tx Data Link” on page 222, “Debugger Reset Circuit” on page 223 and “ISE Interrupt Control” on page 223.
Capture-DR
Shift-DR
Controller State
TDI
Load data at parallel input into shift register stage. Parallel output registers, or latch, retains last state.
Shift data towards serial output. Parallel output register, or latch where provided, retains state.
ADD XXXN
15
15
Table 30. Data Register Operation in Each Controller State
0
0
Figure 80. Bit Allocation Arrangement
ADD XXX(N-1)
15
15
(Continued)
0
0
229
Action
ADD XXX0
15
15
0
0
TDO
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