pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 283

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Module
When handling an ALARM event, make sure that no events are lost by clearing RTCAL bit before clearing the ALARM status
in the RTC.
5.5.3
The MSWC generates four types of output events:
Figure 97 shows the enabling mechanism and the event generation scheme for the various output events. Output events to
the host are generated for input events that have their status bit set (WK_STSn.i is 1). Output events to the core, through
the MIWU, are generated for input events that have their core status bit set (MSHESn.i is 1).
Each of the three Host Wake-Up Event Routing Control registers (WK_ENn, WK_SMIENn and WK_IRQENn) holds a Rout-
ing Enable bit for each event; this allows selective routing of these events to PWUREQ, SMI and/or the assigned MSWC
interrupt request (IRQ) channel, respectively.
After an output event is asserted, it is active until all set status bits are cleared or masked. The current status of the event
may be read at the ACPI status registers in the chipset’s ACPI controller or by reading “Wake-Up Event Status Register 0
(WK_STS0)” on page 286 and “Wake-Up Signals Value Register (WK_SIGV)” on page 288.
As shown in Figure 98, for SMI output events, the MSWC combines the event request coming from the Host Interface’s Pow-
er Management channels 1 and 2 with MSWC internal SMI events.
The SMI may be output from the PC87591L-N05 using the dedicated SMI signal or by routing SMI to an interrupt request
channel via the device’s configuration registers.
The Wake-Up Event Routing Control register, MSHEIEn, which is controlled by the core, holds an enable bit for each of the
events, which allows selective routing of these events to the core wake-up interrupt (MSWCI) to the MIWU. The core event
is controlled using a separate set of status signals to prevent race conditions when clearing events.
The MSWCI interrupt is a level high interrupt that gathers requests from MSHESn, MSWCTL2 and MSWCTL3 registers.
Once an output event is asserted, it keeps its active state until all set status bits are cleared or masked. This interrupt signal
is connected to the MSWC wake-up input of the MIWU. This enables handling state change requests even in Idle mode.
The MSWC output for this input is connected to the core through the MIWU module, enabling a power state change on in-
terrupt.
• IRQ - an interrupt routed as configured in the MSWC PnP configuration registers.
• PWUREQ - an event that is typically connected to an input in the chipset that triggers an SCI event.
• SMI - an event typically connected to an input in the chipset that triggers an SMI event.
• MSWCI - an interrupt to the MIWU module in the core domain. This enables the core firmware to handle the wake-
Wake-Up Event i
Extension Logic
From Wake-Up
up events.
Wake-Up Output Events
Detection
Event i
WK_SMIENn.i
WK_IRQENn.i
WK_ENn.i
MSHEIEn.i
Figure 97. Wake-Up Event Routing Scheme
WK_STSn.i
MSHESn.i
(Continued)
283
Event
Routing
Logic
To Peripheral Bus
to MIWU
MSWCI
PWUREQ
SMI
IRQ
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