pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 230

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Debug Bypass Register (BYPASS)
The BYPASS register provides a minimum length serial path for data movement between TDI and TDO. This path can be
selected when no other data register needs to be accessed.
The BYPASS register consists of a single shift register stage.
When the current instruction selects the BYPASS register for inclusion in the serial path between TDI and TDO, the shift
register stage is set to 0 on the rising edge of TCK following entry into Capture-DR state. The BYPASS register is accessed
from the JTAG serial bus only.
Debug Data Register (DBGDATA)
This register is the shift register element of DBGRXD and DBGTXD. It is accessed from the JTAG serial bus only. Figure 81
shows the parallel load data scheme.
The DBGDATA register consists of shift register stages according to the data buffer length. The actual length of the data value,
in a scan operation, is set before Capture-DR state when the current instruction is SCAN_RX or SCAN_TX. In the first case, it
is set according to SCAN_RX L0 to L4; in the latter case, it is set according to the value of MSG_LEN in DBGTXST register.
The actual length of the register is 16*(length+1), where “length” is the binary positive number created by the length field
(with L4 as MSB).
A length longer than the maximum data buffer is mapped to maximum length. A length shorter than the maximum data buffer
results in loading the data to/from the smallest addresses in the data buffer. Maximum length for this design is 128 shift reg-
ister stages. Note that TDO is always fixed; the TDI “insertion-point” changes according to the actual length.
Debug Abort Mask Register (DBGMASKS)
This is a serial shift register, with parallel output and parallel input (for read and write of ABORT_MASK register), accessed
by the JTAG serial bus while the SCAN_ABORT_MASK instruction is set to TAP IR. The register is not addressable from
the peripheral bus. The non-reserved bits of ABORT_MASK register are preset to 1 on Power-Up reset.
Exit1-DR
Exit2-DR
Pause-DR
Update-DR
All other controller
states
Controller State
DBGDATA
DBGRXD
DBGTXD
Retain last state.
Load parallel output register or latch from the shift register stage. Shift register stage retains state.
Registers that have a parallel output maintain the last state of this output; otherwise undefined.
TDI
Figure 81. DBGDATA Connection to the Data Links
ADD XXE
15
15
15
ADD YYE
0
0
0
(Continued)
ADD XXC
15
15
15
ADD YYC
Length = 8 words
230
0
0
0
Action
ADD XX2
15
15
15
ADD YY2
0
0
0
Length = 1 word
ADD XX0
15
15
15
ADD YY0
0
0
0
TDO
Revision 1.2